NXP Semiconductors MPC5644A, Reference Manual, Page: 593 / 1735

Error Correction Status Module (ECSM)
MPC5644A Microcontroller Reference Manual, Rev. 6
Freescale Semiconductor 593
Table 18-8. ECSM_EEGR field description
Name Description
0
FRCAP
Force RAM Error Injection Access Protection
0 = All Platform masters are able to generate RAM ECC errors via the ECSM_EEGR.
1 = Only the Platform master with ID=0 (usually the core) can generate RAM ECC errors via the
ECSM_EEGR.
The assertion of this bit ensures that RAM data inversions can only occur from the master module with
the master ID of 0. Since this is usually the core, this protects the RAM from errant or multiple
simultaneous attempted data inversions from other master modules and, in the case of a multi-core
system, ensures that only one core can issue a RAM data inversion.
The reset value of the bit is 0 and as a result, RAM data inversions can be requested from any master
module. It is the responsibility of the software to ensure the proper setting of this bit.
2
FRC1BI
1
Force RAM Continuous 1-bit Data Inversions
0 = No RAM continuous 1-bit data inversions are generated.
1 = 1-bit data inversions in the RAM are continuously generated.
The assertion of this bit forces the RAM controller to create 1-bit data inversions, as defined by the bit
position specified in ERRBIT[6:0], continuously on every write operation.
The normal ECC generation takes place in the RAM controller, but then the polarity of the bit position
defined by ERRBIT is inverted to introduce a 1-bit ECC event in the RAM.
After this bit has been enabled to generate another continuous 1-bit data inversion, it must be cleared
before being set again to correctly re-enable the error generation logic.
3
FR11BI
1
Force RAM One 1-bit Data Inversion
0 = No RAM single 1-bit data inversion is generated.
1 = One 1-bit data inversion in the RAM is generated.
The assertion of this bit forces the RAM controller to create one 1-bit data inversion, as defined by the
bit position specified in ERRBIT[6:0], on the first write operation after this bit is set.
The normal ECC generation takes place in the RAM controller, but then the polarity of the bit position
defined by ERRBIT is inverted to introduce a 1-bit ECC event in the RAM.
After this bit has been enabled to generate a single 1-bit data inversion, it must be cleared before
being set again to properly re-enable the error generation logic.
6
FRCNCI
Force RAM Continuous Non-Correctable Data Inversions
0 = No RAM continuous 2-bit data inversions are generated.
1 = 2-bit data inversions in the RAM are continuously generated.
The assertion of this bit forces the RAM controller to create 2-bit data inversions, as defined by the bit
position specified in ERRBIT[6:0] and the overall odd parity bit, continuously on every write operation.
After this bit has been enabled to generate another continuous non-correctable data inversion, it must
be cleared before being set again to properly re-enable the error generation logic.
The normal ECC generation takes place in the RAM controller, but then the polarity of the bit position
defined by ERRBIT and the overall odd parity bit are inverted to introduce a 2-bit ECC error in the
RAM.