NXP Semiconductors MPC5644A, Reference Manual, Page: 1067 / 1735

Enhanced Queued Analog-to-Digital Converter (EQADC)
MPC5644A Microcontroller Reference Manual, Rev. 6
Freescale Semiconductor 1067
Figure 25-43. Alternate Configuration 1-8 Control Registers (ADC_ACR1-8)
ADC0/1 Register address: 0x30
ADC0/1 Register address: 0x34
ADC0/1 Register address: 0x38
ADC0/1 Register address: 0x3C
ADC0/1 Register address: 0x40
ADC0/1 Register address: 0x44
ADC0/1 Register address: 0x48
ADC0/1 Register address: 0x4C
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R RET
_IN
H
0 DEST FMT
A
0 RESSEL 0 0 ATBSEL PRE_GAIN
W
RESET: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
= Unimplemented or Reserved
Table 25-41. Alternate Configuration 1-8 Control Registers (ADC_ACR1-8) field description
Field Description
0
RET_INH
Result Transfer Inhibit / Decimation Filter Pre-Fill
This bit is used to inhibit the transfer of the result data from the peripheral module to the
result queue. When the module is a Decimation Filter, this bit sets the filter in a special mode
(PRE-FILL) in which it does not generate decimated samples out from the conversion results
received from the EQADC block, but the conversion samples are used by the filter algorithm.
This feature allows a proper initialization of the Decimation Filter without generating any
decimated result. Or this bit is useful for sending the result of the ADC to the STAC bus
master but not putting the result in the result queue.
1 No result transfer to result queue / Decimation Filter PRE-FILL mode
0 Result transfer to result queue / Decimation Filter in filtering mode
2-5
DEST
[0:3]
Conversion Result Destination Selection
The DEST[0:3] field selects the destination of the conversion result generated by the
Alternate Conversion Command as shown in
Table 25-42 . This field also affects the behavior
of the FMTA bit and the FFMT bit of the conversion command for alternate configurations
(see
Section , Conversion Command Format for Alternate Configurations ).
6
FMTA
Conversion Data Format for Alternate Configuration
If the DEST field is not 0b000, the FMTA bit specifies how the 12-bit conversion data returned
by the ADCs is formatted into the 16-bit data which is sent to the parallel side interface.
1 Right justified signed
0 Right justified unsigned
8-9
RESSEL
[0:1]
ADC Resolution Selection
The RESSEL[0:1] field selects the resolution of the ADC according to
Table 25-43 .