NXP Semiconductors MPC5644A, Reference Manual, Page: 1347 / 1735

Enhanced Serial Communication Interface (ESCI)
MPC5644A Microcontroller Reference Manual, Rev. 6
Freescale Semiconductor 1347
31.3.2.5 Interrupt Flag and Status Register 1 (eSCI_IFSR1)
This register provides interrupt flags that indicate the occurrence of module events. The related interrupt
enable bits are located in
Control register 1 (eSCI_CR1) and Control register 2 (eSCI_CR2) .
Table 31-9. eSCI_DR field descriptions
Field Description
RN Received Most Significant Bit. The semantic of this bit depends on the frame format selected by
eSCI_CR3[M2], eSCI_CR1[M], and eSCI_CR1[PE].
[M2=0,M=1,PE=0]: value of received data bit 8 or address bit.
[M2=0,M=1,PE=1]: value of received parity bit if eSCI_CR2[PMSK]=0, 0 otherwise.
[M2=1,M=0,PE=1]: value of received parity bit if eSCI_CR2[PMSK]=0, 0 otherwise.
[M2=1,M=1,PE=1]: value of received parity bit if eSCI_CR2[PMSK]=0, 0 otherwise.
It is 0 for all other frame formats.
TN Transmit Most Significant Bit. The semantic of this bit depends on the frame format selected by eSCI_CR3[M2],
eSCI_CR1[M], and eSCI_CR1[PE].
[M2=0,M=1,PE=0]: value to be transmitted as data bit 8 or address bit.
It is not used for all other frame formats.
ERR Receive Error Bit. This bit indicates the occurrence of the errors selected by the Control register 3 (eSCI_CR3)
during the reception of the frame presented in SCI data register (eSCI_DR) . In case of an overrun error for
subsequent frames this bit is set too.
0 None of the selected errors occured.
1 At least one of the selected errors occured.
RD[11:8] Received Data. The semantic of this field depends on the frame format selected by eSCI_CR3[M2] and
eSCI_CR1[M].
[M2=1,M=1]: value of the received data bits 11:8. (Rx=BITx).
It is all 0 for all other frame formats.
RD[7] Received Bit 7. The semantic of this bit depends on the format selected by eSCI_CR3[M2], eSCI_CR1[M], and
eSCI_CR1[PE].
[M2=0,M=0,PE=0]: value of received BIT7 or ADDR BIT.
[M2=0;M=0,PE=1]: value of received PARITY BIT if eSCI_CR2[PMSK]=0, 0 otherwise.
For all other frame formats it is the value of received BIT7.
TD[7] Transmit Bit 7. The semantic of this bit depends on the format selected by eSCI_CR3[M2], eSCI_CR1[M], and
eSCI_CR1[PE].
[M2=0,M=0,PE=0]: value of transmit BIT7 or ADDR BIT.
[M2=0;M=0,PE=1]: not used. PARITY BIT is generated internally before transmission.
For all other frame formats it is the value of transmit BIT7.
RD[6:0] Received bits 6 to 0. Value of received BITx is shown in bit Rx
TD[6:0] Transmit bits 6 to 0. Value of bit Tx is transmitted in BITx
eSC 0x0008 Write: Anytime
R TDRE TC RDRF IDLE OR NF FE PF DACT BERR WACT LACT TACT RACT
W w1c w1c w1c w1c w1c w1c w1c w1c w1c
Reset 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 31-6. Interrupt Flag and Status Register 1 (eSCI_IFSR1)