NXP Semiconductors MPC5644A, Reference Manual, Page: 668 / 1735

Configurable Enhanced Modular IO Subsystem (eMIOS200)
MPC5644A Microcontroller Reference Manual, Rev. 6
668 Freescale Semiconductor
22.5.1.1.5 Input period measurement (IPM) mode
The IPM mode (MODE[0:6] = 0000101) allows the measurement of the period of an input signal by
capturing two consecutive rising edges or two consecutive falling edges. Successive input captures are
done on consecutive edges of the same polarity. The edge polarity is defined by the EDPOL bit in the
EMIOS_CCR[n].
When the first edge of selected polarity is detected, the selected time base is latched into the registers A2
and B2, and the data previously held in register B2 is transferred to register B1. On this first capture the
FLAG line is not set, and the values in registers B1 is meaningless. On the second and subsequent captures,
the FLAG line is set and data in register B2 is transferred to register B1.
When the second edge of the same polarity is detected, the counter bus value is latched into registers A2
and B2, the data previously held in register B2 is transferred to data register B1 and to register A1. The
FLAG bit is set to indicate the start and end points of a complete period have been captured. This sequence
of events is repeated for each subsequent capture. Registers EMIOS_CADR[n] and EMIOS_CBDR[n]
return the values in register A2 and B1, respectively.
In order to allow coherent data, reading EMIOS_CADR[n] forces A1 content be transferred to B1 register
and disables transfers between B2 and B1. These transfers are disabled until the next read of the
EMIOS_CBDR[n]. Reading EMIOS_CBDR[n] forces A1 content to be transferred to B1 and re-enables
transfers from B2 to B1, to take effect at the next edge capture.
The input pulse period is calculated by subtracting the value in B1 from A2.
Figure 22-21 shows how the channel can be used for input period measurement.
Figure 22-21. Input Period Measurement example
Figure 22-22 describes the A1 and B1 register updates when EMIOS_CADR[n] and EMIOS_CBDR[n]
read operations are performed. When EMIOS_CADR[n] read occurs the content of A1 is transferred to B1
thus providing coherent data in A2 and B1 registers. Transfers from B2 to B1 are then blocked until
EMIOS_CBDR[n] is read. After EMIOS_CBDR[n] is read, register A1 content is transferred to register
B1 and the transfers from B2 to B1 are re-enabled to occur at the transfer edges, which is the leading edge
in the
Figure 22-22 example.
selected counter bus 0x000500 0x001000 0x001100 0x001250 0x001525 0x0016A0
A2(captured) value
2
A1 value
B2 (captured) value
0xxxxxxx 0x001000 0x001250
0xxxxxxx 0x001000 0x001250 0x0016A0
0xxxxxxx 0x001000 0x001250 0x0016A0
Input signal
1
EDPOL = 1
FLAG pin register
Notes: 1. After input filter
2. CADR[n] = A2
3. CBDR[n] = B1
A A A
B1 value
3
0xxxxxxx 0x001000 0x001250