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Configurable Enhanced Modular IO Subsystem (eMIOS200)
MPC5644A Microcontroller Reference Manual, Rev. 6
Freescale Semiconductor
669
Figure 22-22. A1 and B1 updates at EMIOS_CADR[n] and EMIOS_CBDR[n] reads
22.5.1.1.6
Double action output compare (DAOC) mode
In the DAOC mode the leading and trailing edges of the variable pulse width output are generated by
matches occurring on comparators A and B. There is no restriction concerning the order in which A and
B matches occur.
When the DAOC mode is entered, exiting from GPIO mode both comparators are disabled and the output
flip-flop is set to the complement of the EDPOL bit in the EMIOS_CCR[n].
Data written to A2 and B2 are transferred to A1 and B1, respectively, on the next system clock cycle if bit
OU[n] of the EMIOS_OUDR is cleared (see
). The transfer is blocked if OU[n] bit is set.
Comparator A is enabled only after the transfer to A1 register occurs and is disabled on the next A match.
Comparator B is enabled only after the transfer to B1 register occurs and is disabled on the next B match.
Comparators A and B are enabled and disabled independently.
The output flip-flop is set to the value of EDPOL when a match occurs on comparator A and to the
complement of EDPOL when a match occurs on comparator B.
MODE[6] controls if the FLAG is set on both matches (MODE[0:6] = 0000111) or just on the B match
(MODE[0:6] = 0000110). FLAG bit assertion depends on comparator enabling.
If subsequent enabled output compares occur on registers A1 and B1, pulses will continue to be generated,
regardless of the state of the FLAG bit.
At any time, the FORCMA and FORCMB bits allow the software to force the output flip-flop to the level
corresponding to a comparison event in comparator A or B, respectively. Note that the FLAG bit is not
affected by these forced operations.
selected counter bus 0x000500
0x001000
0x001100
0x001250
0x001525
0x0016A0
A2(captured) value
2
B2(captured) value
B1 value
3
0xxxxxxx
0x001000
0x001250
0x0016A0
0xxxxxxx
0x001000
0xxxxxxx
0x001000
Input signal
1
A
A
A
FLAG pin/register
EDPOL = 1
A1 value
0xxxxxxx
0x001000
0x001000
0x001250
0x001250
Read CADR[n]
Read CBDR[n]
0x001250
Notes: 1. After input filter
2. CADR[n] = A2
3. CBDR[n] = B1
0x0016A0
Summary of Contents for MPC5644A
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Page 24: ...MPC5644A Microcontroller Reference Manual Rev 6 24 Freescale Semiconductor...
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Page 52: ...Introduction MPC5644A Microcontroller Reference Manual Rev 6 52 Freescale Semiconductor...
Page 56: ...Memory Map MPC5644A Microcontroller Reference Manual Rev 6 56 Freescale Semiconductor...
Page 1228: ...Decimation Filter MPC5644A Microcontroller Reference Manual Rev 6 1228 Freescale Semiconductor...
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