NXP Semiconductors MPC5644A, Reference Manual, Page: 234 / 1735

Flash memory
MPC5644A Microcontroller Reference Manual, Rev. 6
234 Freescale Semiconductor
12.3.2.8 Bus Interface Unit Configuration Register (BIUCR)
The Bus Interface Unit Configuration Register (BIUCR) is used to specify operation of the dual-flash
controller.
Table 12-11. AR field descriptions
Field Description
SAD Shadow Address
The SAD bit qualifies the address captured during an ECC Event Error, Single Bit Correction, or State
Machine operation.
The SAD register is not writable.
0: Address Captured is from Main Array Space.
1: Address Captured is from Shadow Array Space.
ADDR[14:0] Address
The ADDR field provides the first failing address in the event of ECC event error (MCR[EER] set), single
bit correction (MCR[SBC] set), as well as providing the address of a failure that may have occurred in
a state machine operation (MCR[PEG] cleared). ECC event errors take priority over single bit
corrections, which take priority over state machine errors. This is especially valuable in the event of a
RWW operation, where the read senses an ECC error or single bit correction, and the state machine
fails simultaneously. This address is always a Double Word address that selects 64 bits.
The ADDR field is writable, and can be used in the UTEST ECC Logic Check. If the ECC logic check
is enabled (UT0[EIE] = 1) then the AR will not update for ECC event error, single bit correction or state
machine errors.
If MCR[EER] or MCR[SBC] are set, the AR is locked from writing. MCR[PEG] does not affect the
writability of the ADDR field.
Offset: FLASH_REG 0x001C Access: User read/write
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R 0 0 0 0 0 0 0 0 0
M6PFE
0
M4PFE
0 0
M1PFE M0PFE
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
APC WWSC RWSC
0
DP
FEN
0
IF
PFE
N
0
PFLIM
BF
E
N
W
Reset 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0
Figure 12-10. Bus Interface Unit Configuration Register (BIUCR)