NXP Semiconductors MPC5644A, Reference Manual, Page: 1463 / 1735

FlexRay Communication Controller (FlexRay)
MPC5644A Microcontroller Reference Manual, Rev. 6
Freescale Semiconductor 1463
This register is used to trigger write and read operations on the PE data memory (PE DRAM). These
operations are used for memory error injection and memory error observation.
Each write access to this registers initiates a read or write operation on the PE DRAM. The access done
status bit DAD is cleared after the write access and is set if the PE DRAM access has been finished.
In case of an PE DRAM write access, the data provided in PE DRAM Data Register (FR_PEDRDR) are
written into the PE DRAM, read back from the PE DRAM and are stored into the PE DRAM Data Register
(FR_PEDRDR) .
In case of an PE DRAM read access, the requested data are read from PE DRAM and stored into the PE
DRAM Data Register (FR_PEDRDR) .
For a detailed description refer to Section 33.6.24, Memory content error detection ”
33.5.2.10 PE DRAM Data Register (FR_PEDRDR)
This register provides the data to be written to or read from the PE DRAM by the access initiated by write
access to the
PE DRAM Access Register (FR_PEDRAR) .
Table 33-15. FR_PEDRAR field description
Field Description
INST PE DRAM Access Instruction — This field defines the operation to be executed on the PE DRAM.
0011 PE DRAM write: Write FR_PEDRDR[DATA] to PE DRAM address ADDR (16 bit)
0101 PE DRAM read: Read Data from PE DRAM address ADDR (16 bit) into FR_PEDRDR[DATA]
other Reserved
ADDR PE DRAM Access Address — This field defines the address in the PE DRAM to be written to or
read from.
DAD PE DRAM Access Done — This status bit is cleared when the application has written to this
register and is set when the PE DRAM access has finished.
0 PE DRAM access running
1 PE DRAM access done
Base + 0x0012 16-bit write access required Write: Normal Mode
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R
DATA
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 33-10. PE DRAM Data Register (FR_PEDRDR)