Peripheral Bridge (PBRIDGE)
MPC5644A Microcontroller Reference Manual, Rev. 6
206
Freescale Semiconductor
10.4
PBRIDGE signal description
The PBRIDGE has no external signals.
10.5
PBRIDGE functional description
The PBRIDGE functions as a protocol translator. Support is provided for generating a pair of 32-bit slave
bus instruction accesses (not data accesses) when targeted by a 64-bit system bus access.
Accesses which fall within the address space of the PBRIDGE are decoded to provide individual module
selects for peripheral devices.
10.5.1
Read cycles
Two clock read accesses are possible with the PBRIDGE when the requested access size is 32-bits or
smaller, and is not misaligned across a 32-bit boundary. If the requested instruction access size is 64-bits,
then a minimum of three clocks are required to complete the access. Misaligned read accesses are not
supported. 64-bit data reads (not instruction) are not supported.
10.5.2
Write cycles
Three clock write accesses are possible with the PBRIDGE when the requested access size is 32-bits or
smaller, and is not misaligned across a 32-bit boundary. Misaligned writes that do not cross a 32-bit
boundary are supported. 64-bit data writes (not instruction) are not supported.
10.6
Memory map and register description
10.6.1
Memory map
Each register in the PBRIDGE module has a size of 32 bits. The registers are listed in
memory map organization is shown in
. The organizational hierarchy is as follows:
•
The module has multiple registers with the same register name (MPCR, PACR, OPACR), each at
a different address offset.
•
Each register has multiple similarly-named fields, each with a different number.
•
Each field has subfields as defined elsewhere in this section.
Accesses to registers or register fields marked as reserved will return zeros on reads, and will be ignored
on writes.
Table 10-1. PBRIDGE registers
Offset from PBRIDGE_BASE
(0xFFF0_0000)
Register
Location
0x0000–0x0007
1
Master Privilege Control Registers (MPCR)
0x0008–0x001F
Reserved
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