NXP Semiconductors MPC5644A, Reference Manual, Page: 1038 / 1735

Enhanced Queued Analog-to-Digital Converter (EQADC)
MPC5644A Microcontroller Reference Manual, Rev. 6
1038 Freescale Semiconductor
12
RFOFx
RFIFO Overflow Flag x
RFOFx indicates an overflow event on RFIFOx. RFOF
x is set when RFIFOx is already full,
and a new data is received from the on-chip ADCs or from the external device. The RFIFOx
will not overwrite older data in the RFIFO, and the new data will be ignored. When RFOIEx
in
Section 25.5.2.8, EQADC Interrupt and DMA Control Registers (EQADC_IDCR) , and
RFOFx are both asserted, the EQADC generates an interrupt request.
Apart from generating an independent interrupt request for an RFIFOx overflow event, the
EQADC also provides a combined interrupt at which the Result FIFO Overflow Interrupt, the
Command FIFO Underflow Interrupt, and the Command FIFO Trigger Overrun Interrupt
requests of ALL CFIFOs are ORed. When RFOIEx, CFUIEx, and TORIEx are all asserted,
this combined interrupt request is asserted whenever one of the following 18 flags becomes
asserted: RFOFx, CFUFx, and TORFx (assuming that all interrupts are enabled). See
Section 25.6.8, EQADC DMA/Interrupt request , for details.
Write “1” to clear RFOFx. Writing a “0” has no effect.
1 An RFIFO overflow event occurred.
0 No RFIFO overflow event occurred.
14
RFDF x
RFIFO Drain Flag x
RFDFx indicates if RFIFOx has valid entries or not. RFDFx
is set when the RFIFOx has at
least one valid entry in it. When RFDEx in Section 25.5.2.8, EQADC Interrupt and DMA
Control Registers (EQADC_IDCR) , and RFDFx are both asserted, an interrupt or a DMA
request will be generated depending on the status of the RFDSx bit. When RFDSx is
negated (interrupt requests selected), software clears RFDFx by writing a “1” to it. Writing a
“0” has no effect. When RFDSx is asserted (DMA requests selected), RFDFx is
automatically cleared by the EQADC when the RFIFO becomes empty.
1 RFIFOx has at least one valid entry.
0 RFIFOx is empty.
Note: Writing “1” to RFDFx when RFDSx is asserted (DMA requests selected) is not
allowed.
Note: When the generation of interrupt requests is selected (RFDSx=0), RFDFx must only
be cleared in the ISR after the RFIFOx pop register is accessed.
16-19
CFCTRx
[0:3]
CFIFOx Entry Counter
CFCTRx indicates the number of commands stored in the CFIFOx. When the EQADC
completes transferring a piece of new data from the CFIFOx, it decrements CFCTRx by one.
Writing a word or any bytes to the corresponding
Section 25.5.2.5, EQADC CFIFO Push
Registers (EQADC_CFPR) , increments CFCTRx by one. Writing any value to CFCTRx has
no effect.
20-23
TNXTPTRx
[0:3]
CFIFOx Transfer Next Pointer
TNXTPTRx indicates the index of the next entry to be removed from CFIFOx when it
completes a transfer. When TNXTPTRx is zero, it points to the entry with the smallest
memory-mapped address inside CFIFOx. TNXTPTRx is only updated when a command
transfer is completed. If the maximum index number (CFIFO depth minus one) is reached,
TNXTPTRx is wrapped to zero, else, it is incremented by one. For details refer to
Section 25.6.4.1, CFIFO Basic Functionality . Writing any value to TNXTPTRx has no effect.
Table 25-15.
EQADC
FIFO and Interrupt Status Register x (
EQADC
_FISRx) field description (continued)
Field Description