NXP Semiconductors MPC5644A, Reference Manual, Page: 170 / 1735

Enhanced Direct Memory Access Controller (eDMA)
MPC5644A Microcontroller Reference Manual, Rev. 6
170 Freescale Semiconductor
225–230 /
0x1C [1:6]
BITER
[0:5]
or
BITER.LINKCH[0:5
]
Starting major iteration count or link channel number
If channel-to-channel linking is disabled (EDMA_TCD[BITER.E_LINK] = 0),
then
• No channel-to-channel linking (or chaining) is performed after the inner minor
loop is exhausted. TCD bits [225:239] are used to form a 15-bit BITER field.
Otherwise,
• After the minor loop is exhausted, the DMA engine initiates a channel service
request at the channel, defined by BITER.LINKCH[0:5], by setting that
channel’s EDMA_TCD[START] bit.
Note: When the TCD is first loaded by software, this field must be set equal to
the corresponding CITER field. Otherwise, a configuration error is
reported. As the major iteration count is exhausted, the contents of this
field is reloaded into the CITER field.
231–239 /
0x1C [7:15]
BITER
[6:14]
Starting major iteration count
As the transfer control descriptor is first loaded by software, this field must be
equal to the value in the CITER field. As the major iteration count is exhausted,
the contents of this field are reloaded into the CITER field.
Note: If the channel is configured to execute a single service request, the initial
values of BITER and CITER should be 0x0001.
240–241 /
0x1C
[16:17]
BWC
[0:1]
Bandwidth control
This two-bit field provides a mechanism to effectively throttle the amount of bus
bandwidth consumed by the eDMA. In general, as the eDMA processes the
inner minor loop, it continuously generates read/write sequences until the minor
count is exhausted. This field forces the eDMA to stall after the completion of
each read/write access to control the bus request bandwidth seen by the system
bus crossbar switch (XBAR).
00 No DMA engine stalls
01 Reserved
10 DMA engine stalls for 4 cycles after each r/w
11 DMA engine stalls for 8 cycles after each r/w
242–247 /
0x1C
[18:23]
MAJOR.LINKCH
[0:5]
Link channel number
If channel-to-channel linking on major loop complete is disabled
(EDMA_TCD[MAJOR.E_LINK] = 0) then,
• No channel-to-channel linking (or chaining) is performed after the outer major
loop counter is exhausted.
Otherwise
• After the major loop counter is exhausted, the DMA engine initiates a channel
service request at the channel defined by MAJOR.LINKCH[0:5] by setting
that channel’s EDMA_TCD[START] bit.
248 /
0x1C [24]
DONE Channel done
This flag indicates the eDMA has completed the outer major loop. It is set by the
DMA engine as the CITER count reaches zero; it is cleared by software or
hardware when the channel is activated (when the DMA engine has begun
processing the channel, not when the first data transfer occurs).
Note: This bit must be cleared to write the MAJOR.E_LINK or E_SG bits.
Table 8-20. TCDn field descriptions (continued)
Bits /
Word offset
[n:n]
Name Description