
Configurable Enhanced Modular IO Subsystem (eMIOS200)
MPC5644A Microcontroller Reference Manual, Rev. 6
Freescale Semiconductor
683
The IPF is a 5-bit programmable up counter that is incremented by the selected clock source, according to
bits IF[0:3] in EMIOS_CCR[n].
Figure 22-39. lnput programmable filter submodule diagram
The input signal is synchronized by system clock. When a state change occurs in this signal, the 5-bit
counter starts counting up. As long as the new state is stable on the pin, the counter remains incrementing.
If a counter overflows occurs, the new pin value is validated. In this case, it is transmitted as a pulse edge
to the edge detector. If the opposite edge appears on the pin before validation (overflow), the counter is
reset. At the next pin transition, the counter starts counting again. Any pulse that is shorter than a full range
of the masked counter is regarded as a glitch and it is not passed on to the edge detector. A timing diagram
of the input filter is shown in
Figure 22-40. Input programmable filter example
The filter is not disabled during either freeze state or negated GTBE input.
22.5.1.3
Clock prescaler (CP)
The CP divides the GCP output signal to generate a clock enable for the internal counter of the Unified
Channels. The GCP output signal is prescaled by the value defined in the UCPRE[0:1] bits in the
EMIOS_CCR[n]. The prescaler is enabled by setting the UCPREN bit in the EMIOS_CCR[n] and can be
stopped at any time by clearing this bit, thereby stopping the internal counter in the channel.
In order to ensure safe working and avoid glitches the following steps must be performed whenever any
update in the prescaling rate is desired:
1. Write ‘0’ at both bit EMIOS_MCR[GPREN] and UCPREN bit in EMIOS_CCR[n], thus disabling
prescalers;
IF3
filter out
ipg_clk
Prescaled Clock
IF2
IF1
IF0
clk
FCK
EMIOSI
5-bit up counter
synchronizer
clock
Time
selected clock
EMIOSI
5-bit counter
filter out
IF[0:3] = 0010
Summary of Contents for MPC5644A
Page 2: ...MPC5644A Microcontroller Reference Manual Rev 6 2 Freescale Semiconductor...
Page 24: ...MPC5644A Microcontroller Reference Manual Rev 6 24 Freescale Semiconductor...
Page 26: ...MPC5644A Microcontroller Reference Manual Rev 6 26 Freescale Semiconductor...
Page 52: ...Introduction MPC5644A Microcontroller Reference Manual Rev 6 52 Freescale Semiconductor...
Page 56: ...Memory Map MPC5644A Microcontroller Reference Manual Rev 6 56 Freescale Semiconductor...
Page 1228: ...Decimation Filter MPC5644A Microcontroller Reference Manual Rev 6 1228 Freescale Semiconductor...
Page 1440: ...FlexCAN Module MPC5644A Microcontroller Reference Manual Rev 6 1440 Freescale Semiconductor...