NXP Semiconductors MPC5644A, Reference Manual, Page: 1383 / 1735

Enhanced Serial Communication Interface (ESCI)
MPC5644A Microcontroller Reference Manual, Rev. 6
Freescale Semiconductor 1383
31.4.6.5.4 Fast bit error detection
Fast Bit Error Detection has been designed to allow flagging of LIN bit errors while they occur, rather than
flagging them after a byte transmission has completed (see
Figure 31-40 ).
Figure 31-40. Fast Bit Error Detection on a LIN Bus
If fast bit error detection bit FBR in the Control register 2 (eSCI_CR2) is set the eSCI will compare the
transmitted and the received data stream while the transmitter is active (not idle). Once a mismatch
between the transmitted data and the received data is detected the following actions are performed the bit
error flag BERR will be set.
To adjust to different bus loads the sample point at which the incoming bit is compared to the one which
was transmitted can be selected with the BESM bit in the
Control register 2 (eSCI_CR2) . If
eSCI_CR2[BESM] = 1, the comparison will be performed with sample RS13, otherwise with RS9 (see
Figure 31-41 ) (also see Section 31.4.5.3.13, Bit sampling ).
Figure 31-41. Timing Diagram Fast Bit Error Detection
NOTE
To calculate the exact position of the sample point with regard to the RX pin,
the delays through the pads and the two Bus Clock cycle delay through the
input synchronizer also needs to be taken into account.
TXD Pin
RXD Pin
LIN Physical Interface
Synchronizer Stage
Bus Clock
Receive Shift
Register
Transmit Shift
Register
LIN Bus
Compare
Sample Point
Bit Error
Output Transmit
Shift Register
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
Input Receive
Shift Register
eSCI_CR2[BESM] = 0 eSCI_CR2[BESM] = 1
Compare Sample Points