NXP Semiconductors MPC5644A, Reference Manual, Page: 714 / 1735

Reaction Module (REACM)
MPC5644A Microcontroller Reference Manual, Rev. 6
714 Freescale Semiconductor
Figure 23-17. REACM Modulation Minimum Pulse Width Register (REACM_MINPWD)
23.3.16 REACM Modulation Control Word Bank Registers (REACM_MWBK)
The REACM Modulation Control Word Bank Registers (REACM_MWBK) are a set of registers that
controls the Reaction Channel Modulation scheme. These registers are programmed by software and read
by the reaction channels. All the information required by the reaction channels to perform a modulation is
stored in these words. All channels have access to the same words thus sharing of Modulation Words
among channels is possible in this architecture.
Figure 23-18. REACM Modulation Control Word Bank Registers (REACM_MWBK)
Address: REACM_BASE (0xC3FC_7000) + (from 0x06C0) Access: User read/write
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R
W
Reset
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
MIN_PWD[11:0]
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Table 23-19. REACM_MINPWD field descriptions
Field Description
0–19 Reserved, should be cleared.
20–31
MIN_PWD[11:0]
Minimum Pulse Width
The MIN_PWD[11:0] field defines the minimum pulse width allowed by the channel
PWM generation. The checking is performed by the channel hold-off timer. If
MIN_PWD[11:0] = 0x00 then no checking is done even for maximum pulse width or
minimum pulse width.
Note: The MIN_PWD value should be calculated considering the prescaler settings
used for the HOLD_OFF counter.For a programmed MIN_PWD value, a pulse
wider than (M 1) does not set the SCDF flag.
Address: REACM_BASE (0xC3FC_7000) + (from 0x0700 to 0x072C) Access: User read/write
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R
LOOP
IO
SS
0
MM[1:0]
0
SM[1:0]
0
HOD[2:0]
0
LOD[2:0]
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R 0
THRESPT[5:0] STPT[3:0]
0
HDOFFTPT[3:0]
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0