NXP Semiconductors MPC5644A, Reference Manual, Page: 208 / 1735

Peripheral Bridge (PBRIDGE)
MPC5644A Microcontroller Reference Manual, Rev. 6
208 Freescale Semiconductor
10.6.2 Register descriptions
10.6.2.1 Master privilege control registers (MPCR)
Each MPCR register contains one or more 4-bit fields, called MPCR n , as shown in Table 10-2 . Each of
these fields defines the access privilege level associated with bus master n in the platform as well as
specifies whether write accesses from this master are bufferable. The registers provide one field per bus
master. See the “Logical master IDs” section in the XBAR chapter for a list of master numbers and names.
Each MPCR n field has the structure described in Figure 10-2 and Table 10-3 .
Figure 10-2. MPCRn field structure
0 1 2 3
R 0 MTR MTW MPL
W
Reset
0 1 1 1
Table 10-3. MPCRn field structure descriptions
Subfield Description
MTR Master Trusted for Reads
This bit determines whether the master is trusted for read accesses.
0 This master is not trusted for read accesses.
1 This master is trusted for read accesses.
MTW Master Trusted for Writes
This bit determines whether the master is trusted for write accesses.
0 This master is not trusted for write accesses.
1 This master is trusted for write accesses.
MPL Master Privilege Level
This bit determines how the privilege level of the master is determined.
0 Accesses from this master are forced to user-mode.
1 Accesses from this master are not forced to user-mode.
Table 10-4. MPCR register fields
Register Master name Reset value
MPCR 0 z4 core (instr load/store) 0b0111, meaning
MTR = 1
MTW = 1
MPL = 1
MPCR 4 DMA
MPCR 6 FlexRay
MPCR 7 EBI
MPCR 8 z4 core Nexus