NXP Semiconductors MPC5644A, Reference Manual, Page: 846 / 1735

Enhanced Time Processing Unit (eTPU2)
MPC5644A Microcontroller Reference Manual, Rev. 6
846 Freescale Semiconductor
MatchA and MatchB Registers
MatchA and MatchB registers hold a match value to be compared against the selected channel time base.
A match value can only be written into the Match register by microcode, through ERTA/B microengine
registers (see
Section 24.5.9.3.5, Write Channel Match and UDCM Registers ). Microcode can also read
the Match register as a special T4ABS source operation, when T4ABS = 0101, and the source for T4ABS
is selected from the second register set. In this operation, MatchA/B registers are copied into ERTA/B
registers (see
Section 24.5.9.2.2, Selecting sources and destination ). For more information on time base
matches, see Section 24.5.5.2, Match Recognition .
CaptureA and CaptureB Registers
CaptureA and CaptureB registers capture the selected channel time base. CaptureA/B registers cannot be
directly written or read by microcode. During the Time Slot Transition (TST) or during CHAN assignment,
CaptureA/B registers are copied into ERTA/B microengine registers. For more information, see
Section 24.5.5.3, Transition Detection and Time Base Capture .
TBSA and TBSB – Time Base Selection Registers
TBSA/B are 3-bit registers which have the following effect on channel configuration:
• Selection of the timebase (TCR1 or TCR2) to be compared against the match values in MatchA
and/or MatchB registers.
Table 24-41. Event Registers microcode accesses
Register Access Type
Sampled from
channel
Update to
channel
Microcode
fields
1
1
See Section 24.5.9, Microinstruction set .
Reset
value
2
2
n.a. means that value of the register is undetermined after reset.
CaptureA, CaptureB read through ERTA/B to ERTA/B on
CHAN assignment
no T2ABD n.a.
MatchA, MatchB read and write through ERTA/B to ERTA/B
by microcode
from ERTA/B
by microcode
ERWA,
CMW,
ERWB,
T4ABS
n.a.
MRLEA, MRLEB write to 0 (negate) directly;
write to 1 (assert) upon
MatchA/B update from ERTA/B
no immediate MRLE,
ERWA,
ERWB
0, 0
TBSA, TBSB write only no immediate TBSA,
TBSB
000,
000
MRLA, MRLB flag test on branch,
write to 0 (negate) only
on CHAN
assignment
immediate BCC (test)
MRLA,
MRLB
(reset)
0, 0
TDLA, TDLB flag test on branch,
write to 0 (negate) only
on CHAN
assignment
immediate BCC (test)
TDL (reset)
0, 0
TCCEA write only no immediate MTD 0