NXP Semiconductors MPC5644A, Reference Manual, Page: 753 / 1735

Enhanced Time Processing Unit (eTPU2)
MPC5644A Microcontroller Reference Manual, Rev. 6
Freescale Semiconductor 753
— Identical, orthogonal channels, except for channel 0: each channel can perform any time
function. Each time function can be assigned to more than one channel at a given time, so each
signal can have any functionality. Channel 0 has the same capabilities of the others, but can also
work with special Angle Counter logic (see below).
— Link Service Request allows activation of a Channel function by request of another channel,
even between eTPU engines.
— Host Service Request allows activation of a Channel function by Host CPU request
— Each channel has an event mechanism which supports single and double action functionality
in various combinations. It includes two 24-bit capture registers, two 24-bit match registers,
24-bit greater-equal and equal-only comparators.
• 2 independent 24-bit time bases for channel synchronization:
— First time base clocked by system clock with programmable prescaler division from 1 to 512
(in steps of 2), or by output of second time base prescaler.
— First time base can also be clocked by external signal with programmable prescaler division of
1 to 256.
— Second time base clocked by external signal with programmable prescaler division from 1 to
64.
— Second time base external clock source can be replaced by system clock divided by 8.
— Both time bases can be exported or imported via Shared Time and Counter) bus.
— Second time base counter can work as an Angle counter, enabling angle based applications to
match angle instead of time.
— Second time base can also be used as a pulse accumulator gated by external signal.
• Event-Triggered VLIW processor (microengine):
— 2 stage pipeline implementation (fetch and execution), with separate instruction memory -
SCM - and data memory - SPRAM (Harvard architecture)
— Fixed-length instruction execution in two system clock microcycle
— Interleaved SCM access in dual eTPU engine avoids contention in time for instruction memory
— SCM address space of up to 16K positions (64 Kbytes)
— SPRAM with interleaved access in dual eTPU engine avoids contention for data memory
— SPRAM address space of up to 8 Kbytes (both engines).
— Instruction set with embedded Channel support, including specialized Channel control
subinstructions and conditional branching on Channel-specific flags.
— Channel-oriented addressing: channel-bound address mode with Host configured Channel
Base Address allows channel data isolation, independent of microengine application code.
— Channel-bound data address space of up to 128 32-bit parameters (512 bytes)
— Global parameter address mode allows access to common Channel data of up to 256 32-bit
parameters (1024 bytes)
— Support for indirect and stacked data access schemes.
— Parallel execution of: data access, ALU, Channel control and flow control subinstructions in
selected combinations.