NXP Semiconductors MPC5644A, Reference Manual, Page: 116 / 1735

Operating Modes and Clocking
MPC5644A Microcontroller Reference Manual, Rev. 6
116 Freescale Semiconductor
The hold time for external bus pins can be changed by writing to SIU_ECCR[EBTS] (external bus tap
select bit).
NOTE
The CLKOUT pin is only available in the 324-pin package.
5.3.4.6.3 Nexus Message Clock (MCKO)
The Nexus message clock (MCKO) divider can be programmed to divide the system clock by two, four or
eight based on the MCKO_DIV field in the port configuration register (PCR) in the Nexus port controller
(NPC). The reset value of NPC_PCR[MCKO_DIV] selects an MCKO clock frequency one half of the
system clock frequency. The MCKO divider is configured by writing to the NPC through the JTAG port.
5.3.4.6.4 Engineering Clock Divider (ENGDIV)
The engineering clock divider (ENGDIV) can be programmed to divide system clock. This clock is mainly
used to clock some ASIC devices integrated on the board. There is no timing relation of this clock with
respect to any other clock in the design.
Refer to Section 16.6.26, External Clock Control Register (SIU_ECCR) for ENGDIV register bit
programming.
5.3.4.6.5 FlexCAN Clock Divider (CAN2:1)
The FlexCAN module has the ability to run from the system clock. It is possible, at the input to the
FlexCAN module, to perform a divide-by-1 or a divide-by-2 division of the system clock.
This FlexCAN system clock divider can be programmed by configuring the FlexCAN2:1 mode bit (field
SIU_SYSDIV[CAN_SRC]). The reset value is to divide-by-1.
The FlexCAN module does not support a divide-by-1 of the system clock above a certain frequency,
defined in the devicedatasheet. When running at maximum system frequency this setting will have to be
adjusted from its default value.