NXP Semiconductors MPC5644A, Reference Manual, Page: 1373 / 1735

Enhanced Serial Communication Interface (ESCI)
MPC5644A Microcontroller Reference Manual, Rev. 6
Freescale Semiconductor 1373
Start bit qualification
To adjust for baud rate mismatch, the cyclic receive sample counter RSC is re-synchronized after a
successful start bit qualification.
A start bit is successfully qualified if
• the start qualification is active, and
• a low sample is read, and
• the low sample was preceded by three consecutive high samples.
The start bit qualification becomes active
• after module reset, or
• after receiver disable and subsequent enable, or
• after the 7-th sample if the start bit verification failed, or
• after the 10-th sample of last stop bit of the preceding frame (example shown in Figure 31-32 ).
The start bit qualification becomes inactive
• after successful start bit qualification.
Start bit verification
After the successful start bit qualification the receiver starts to verify the start bit by a two out of three
samples majority voting.
A start bit is verified if at least two out of the three sample RSC3, RSC5, and RSC7 are sampled low. Noise
is detected when exactly one out of the three samples is high. In this case, the noise flag eSCI_IFSR1[NF]
is set. The result of the start bit verification is summarized in
Table 31-32 .
If the start bit verification was not successful , the receiver activates the start bit qualification. If the start
bit verification was successful , the receiver continues sampling to perform data noise detection on the
samples at RSC8, RSC9, and RSC10. The result of the start bit data noise detection is summarized in
Table 31-33 . If noise is detected, the noise flag eSCI_IFSR1[NF] is set.
Table 31-32. Start Bit Verification Result
[RSC3, RSC5, RSC7] Start Bit Verified Verification Noise Detected
000 Yes No
001 Yes Yes
010 Yes Yes
100 Yes Yes
011 No No
101 No No
110 No No
111 No No