NXP Semiconductors MPC5644A, Reference Manual, Page: 610 / 1735

System Timer Module (STM)
MPC5644A Microcontroller Reference Manual, Rev. 6
610 Freescale Semiconductor
19.4.2.3 STM Channel n Control Register (STM_CCRn)
The STM Channel n Control Register (STM_CCRn) has the enable bit for channel n of the timer.
19.4.2.4 STM Channel n Interrupt Register (STM_CIRn)
The STM Channel n Interrupt Register (STM_CIRn) has the interrupt flag for channel n of the timer.
Table 19-3. STM_CNT field description
Field Description
CNT Timer count value used as the time base for all channels
When enabled, the counter increments at the rate of the system clock divided by the prescale value.
Offset 0x10+0x10*n Access: Read/Write
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R 0 0 0 0 0 0 0 0 0 0 0
0
0 0 0
CEN
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 19-3. STM Channel Control Register (STM_CCRn)
Table 19-4. STM_CCRn field description
Field Description
CEN Channel Enable
0 = The channel is disabled.
1 = The channel is enabled.