NXP Semiconductors MPC5644A, Reference Manual, Page: 1417 / 1735

FlexCAN Module
MPC5644A Microcontroller Reference Manual, Rev. 6
Freescale Semiconductor 1417
32.4.5.9 Interrupt Masks 2 Register (IMRH)
This register allows any number of a range of 32 Message Buffer Interrupts to be enabled or disabled. It
contains one interrupt mask bit per buffer, enabling the CPU to determine which buffer generates an
interrupt after a successful transmission or reception (i.e. when the corresponding bit in the IFRH register
is set).
Figure 32-13. Interrupt Masks 2 Register (IMRH)
ERRINT Error Interrupt
This bit indicates that at least one of the Error Bits (bits 16–21) is set. If the corresponding mask
bit (CR[ERRMSK]) is set, an interrupt is generated to the CPU. This bit is cleared by writing it to
‘1’.Writing ‘0’ has no effect.
1: Indicates setting of any Error Bit in the Error and Status Register
0: No such occurrence
WAKINT Wake-Up Interrupt
When FlexCAN is in Stop Mode and a recessive to dominant transition is detected on the CAN bus
and if MCR[WAK_MSK] is set, an interrupt is generated to the CPU. This bit is cleared by writing
it to ‘1’. Writing ‘0’ has no effect.
1: Indicates a recessive to dominant transition received on the CAN bus when the FlexCAN
module is in Stop Mode
0: No such occurrence
Base + 0x0024
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R
BUF
63M BUF
62M
BUF
61M BUF
60M BUF
59M BUF
58M
BUF
57M BUF
56M BUF
55M BUF
54M BUF
53M BUF
52M BUF
51M BUF
50M BUF
49M BUF
48M
W
RESET: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
BUF
47M BUF
46M
BUF
45M BUF
44M BUF
43M BUF
42M
BUF
41M BUF
40M BUF
39M BUF
38M BUF
37M BUF
36M BUF
35M BUF
34M BUF
33M BUF
32M
W
RESET: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Table 32-13. IMRH Register field descriptions
Field Description
BUF63M–
BUF32M
Buffer MB
i
Mask
Each bit enables or disables the respective FlexCAN Message Buffer (MB32 to MB63) Interrupt.
1: The corresponding buffer Interrupt is enabled
0: The corresponding buffer Interrupt is disabled
Note: Setting or clearing a bit in the IMRH register can assert or negate an interrupt request, if the
corresponding bit in the IFRH register is set.
Table 32-12. ESR Register field descriptions
Field Description