NXP Semiconductors MPC5644A, Reference Manual, Page: 399 / 1735

System Integration Unit (SIU)
MPC5644A Microcontroller Reference Manual, Rev. 6
Freescale Semiconductor 399
Figure 16-13. IRQ Digital Filter Register (SIU_IDFR)
16.6.14 IRQ Filtered Input Register (SIU_IFIR)
The SIU_IFIR is a read-only register used to capture the filtered values of the IRQ0–31 pins. This feature
is enabled with a parameter at the top level of the module.
The MSB positions of the register correspond to NMI pins and the number of NMI pins are defined by a
parameter.
The LSB positions of the register corresponds to the IRQ pins and the number of IRQ pins is defined by a
parameter.
SI 0x30
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
0 0 0 0 0 0 0 0 0 0 0 0 DFL[0–3]
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
= Unimplemented or Reserved
Table 16-17. SIU_IDFR field description
Field Description
DFL[0–3] Digital Filter Length
This field defines the digital filter period on the IRQ
x inputs according to Equation 16-1 :
Eqn. 16-1
For a 100 MHz system clock, this gives a range of 20 ns to 328 µs. The minimum time of two clocks
accounts for synchronization of the IRQ input pins with the system clock.
Using the same calculation, for a 150 MHz system clock, this gives a range of 13.3 ns to 218 µs.
Filter Period S

ystemClockPeriod 2
DFL
 
1 S

ystemClockPeriod

+ =