NXP Semiconductors MPC5644A, Reference Manual, Page: 920 / 1735

Enhanced Time Processing Unit (eTPU2)
MPC5644A Microcontroller Reference Manual, Rev. 6
920 Freescale Semiconductor
result[23:0] = adder_output[24:1] xor 0x800000
endif
Shift left:
result[23:1] = adder_output[22:0]
result[0] = 0
Rotate right:
case(opsize/CCSV)
8-bit:
result[6:0] = adder_output[7:1]
result[7] = adder_output[0]
result[23:8] = adder_output[23:8]
16-bit:
result[14:0] = adder_output[15:1]
result[15] = adder_output[0]
result[23:16] = adder_output[23:16]
24-bit:
result[22:0] = adder_output[23:1]
result[23] = adder_output[0]
NOTE
Only for the Post-ALU rotate right, the operation size is determined by the
field CCSV (see
Section 24.5.9.2.3, Flags sampling control ). For example:
if CCSV = 00, T4ABS = P (24-bits), T4BBS = A (24 bits), T2ABD = B (24
bits), and ALUOP = “Add ROR”, then B gets A+ P with bits 7:0 rotated,
even though the operation size is 24 bits.
Table 24-64 describes Carry flag behavior.
Table 24-64. Carry flag update on ADD operation
BINV
1
Operation size Shift/rotate Value
1 8 bits none adder carry from bit 7 to bit 8
1 16 bits none adder carry from bit 15 to bit 16
1 24 bits none alu_adder_output[24]
0 8 bits none !adder carry from bit 7 to bit 8
0 16 bits none !adder carry from bit 15 to bit 16
0 24 bits none !alu_adder_output[24]
0 or 1 8 bits shift left alu_adder_output[7]
0 or 1 16 bits shift left alu_adder_output[15]
0 or 1 24 bits shift left alu_adder_output[23]
0 or 1 x shift right alu_adder_output[0]
1 8 bits rotate right adder carry from bit 7 to bit 8
1 16 bits rotate right adder carry from bit 15 to bit 16
1 24 bits rotate right alu_adder_output[24]