NXP Semiconductors MPC5644A, Reference Manual, Page: 915 / 1735

Enhanced Time Processing Unit (eTPU2)
MPC5644A Microcontroller Reference Manual, Rev. 6
Freescale Semiconductor 915
24.5.8.1 Registers
eTPU microengine accesses a total of 18 registers. Fourteen of them are special purpose (registers A, B,
C and D are for general use). Special purpose registers except CHAN and LINK can also be used as general
use if the operation that use their contents are not performed. Register description is intended to just
introduce their functionalities and not to provide detailed explanation of it since it will be described in
Section 24.5.9, Microinstruction set . Registers less than 24 bits in size are right-justified.
None of the registers have guaranteed reset values. However, some are initialized just before the thread
starts (see
Section 24.5.1.2, Time slot transition ).
24.5.8.1.1 P Register
P register is the only one that is 32-bit wide. It can be used as source and destination for arithmetic/logical
operation, and as source and destination for SPRAM read/write operations.
For P source/destination possibilities in ALU/MDU microoperations, see Section 24.5.9.2.2, Selecting
sources and destination .
When P is used as SPRAM read/write operations source or destination there are only 3 possibilities of
access: all 32 bits, lower 24 bits and upper 8 bits. SPRAM operations are explained in detail in
Section 24.5.9.1, SPRAM microoperations .
P is automatically loaded with one parameter before the thread starts (parameter preload). For more
information see
Section 24.5.1.1.5, Entry point format , and Section 24.5.1.2, Time slot transition .
Upper 8 bits of P register can be used as application state, since these bits can be tested as branch
conditions. P[31:24] is also used in dispatch microoperation (see
Section 24.5.9.4.3, Dispatch
microoperation ), and bit pairs P[29:28], P[27:26], P[25:24] can be directly copied into Channel flags 1 and
0 using field FLC. Together with Entry Table Condition Encoding, it provides fast state resolution without
code execution.
24.5.8.1.2 DIOB – Data Input/Output Buffer Register
The DIOB register is 24-bit wide and can be used as source and destination for arithmetic/logical
operations as well as SPRAM data source and destination. The DIOB only can be accessed as 24 bits, both
in arithmetic/logical and SPRAM read/write operations. When using the DIOB to perform an SPRAM
access, only the lower 24 bits of SPRAM will be accessible (SPRAM upper 8 bits always remain
unchanged).
The DIOB can also be used as SPRAM addressing register, when the DIOB contents are used as absolute
SPRAM address (14-bit wide). In this case the DIOB can also be pre-decremented or post-incremented
(see
Section , Indirect addressing mode ).
The DIOB is automatically loaded with one parameter before the thread starts (parameter preload). For
more information see
Section 24.5.1.1.5, Entry point format , and Section 24.5.1.2, Time slot transition .