NXP Semiconductors MPC5644A, Reference Manual, Page: 85 / 1735

Signal Description
MPC5644A Microcontroller Reference Manual, Rev. 6
Freescale Semiconductor 85
3.2 Signal Details
Table 2. Pad types
Pad Type I/O Voltage Range
Slow 3.0V - 5.5 V
Medium 3.0 V - 5.5 V
Fast 3.0 V - 3.6 V
MultiV
1,2
1
Multivoltage pads are automatically configured in low swing mode
when a JTAG or Nexus function is selected, otherwise they are high
swing.
2
VDDEH7 supply cannot be below 4.5 V when in low-swing mode.
3.0 V - 5.5 V (high swing mode)
3.0 V - 3.6 V (low swing mode)
Analog 0.0 - 5.5 V
LVDS —
Table 3-3. Signal details
Signal Module or Function Description
CLKOUT Clock Generation MPC5644A clock output for the external/calibration bus
interface
ENGCLK Clock Generation Clock for external ASIC devices
EXTAL Clock Generation Input pin for an external crystal oscillator or an external clock
source based on the value driven on the PLLREF pin at reset.
PLLREF Clock Generation
Reset/Configuration PLLREF is used to select whether the oscillator operates in xtal
mode or external reference mode from reset. PLLREF=0 selects
external reference mode. On the 324BGA package, PLLREF is
bonded to the ball used for PLLCFG[0] for compatibility with
MPC55xx devices .
For the 176-pin QFP and 208-ball BGA packages:
0: External reference clock is selected.
1: XTAL oscillator mode is selected
For the 324 ball BGA package:
If RSTCFG is 0:
0: External reference clock is selected.
1: XTAL oscillator mode is selected.
If RSTCFG is 1, XTAL oscillator mode is selected.
XTAL Clock Generation Crystal oscillator input
DSPI_B_SCK_LVDS-
DSPI_B_S DSPI LVDS pair used for DSPI_B TSB mode transmission