NXP Semiconductors MPC5644A, Reference Manual, Page: 949 / 1735

Enhanced Time Processing Unit (eTPU2)
MPC5644A Microcontroller Reference Manual, Rev. 6
Freescale Semiconductor 949
TDL can be one or two bits wide, depending on the microinstruction format (see Section 24.5.9.7,
Microinstruction formats ). Two-bit TDL allows independent clearing of TDLA and/or TDLB.
Table 24-104 defines the two-bit TDL field.
24.5.9.3.7 Disable matches
Microcode field MRLE (1 bit) allows disabling matches on channel selected by CHAN register, for both
MatchA and MatchB registers, by clearing their respective MRLE bits. Matches can be enabled for each
Match register using ERWA and ERWB fields (see
Section 24.5.9.3.5, Write Channel Match and UDCM
Registers ).
Some instruction formats have a two-bit MRLE field (see Section 24.5.9.7, Microinstruction formats )
which allows independent disabling of Matches 1 and 2, as shown in Table 24-106 .
Table 24-103. Clear Transition/Match Event Registers – MRLA/B, TDL
Field Meaning
MRLA 0 = clear MRLA event register, 1 = don’t change
MRLB 0 = clear MRLB event register, 1 = don’t change
TDL (1 bit) 0 = clear TDLA and TDLB flags, 1 = don’t change
Table 24-104. Independent TDLA/B clear – two-bit TDL
Value Meaning
0 0 clear TDLA
0 1 clear TDLB
1 0 clear both TDLA and TDLB
1 1 do not clear TDLA or TDLB
Table 24-105. Disable Matches – MRLE
MRLE Meaning
0 Disable matches for Match A and Match B
1 don’t change match enabling
Table 24-106. Two-bit MRLE
MRLE Meaning
0 0 Disable Match A (clear MRLEA)
0 1 Disable both Matches (clear MRLEA and
MRLEB)
1 0 Disable Match B (clear MRLEB)
1 1 nop