Deserial Serial Peripheral Interface (DSPI)
MPC5644A Microcontroller Reference Manual, Rev. 6
1320
Freescale Semiconductor
30.9.10.7 SPI frame parity error interrupt request
The SPI Frame Parity Error Flag indicates that a SPI frame with parity error had been received. The
SPEFRE bit in the DSPI_RSER must be set for the interrupt request to be generated.
30.9.10.8 DSI frame parity error interrupt request
The DSI Frame Parity Error Flag indicates that a DSI frame with parity error has been received. The
DPEFRE bit in the DSPI_RSER must be set for the interrupt request to be generated.
30.9.10.9 Deserialized data match interrupt request
The Deserialized Data Match Flag (DDIF) indicates that a DSI frame with data matches DSPI_DPIR data,
masked with DSPI_DIMR, had been received. The DDIFRE bit in the DSPI_RSER must be set for the
interrupt request to be generated.
30.9.11 Buffered SPI operation
The DSPI can use a FIFO buffering mechanism to transmit and receive commands and data to and from
external devices. The Transmit FIFO buffers SPI commands and data to be transferred. The Receive FIFO
buffers incoming serial data. Both FIFOs are four entries deep. The TX FIFO stores 32-bit words when the
DSPIs are configured for Master Mode. The 32-bit words are composed of 16-bit command fields and data
fields up to 16 bits wide. The RX FIFOs store 16-bit words of received data from external devices. When
the DSPI is configured for Slave Mode, the DSPI ignores the SPI command in the TX FIFO.
For queued operations, the SPI queues reside in system memory external to the DSPI. Data transfers
between the memory and the DSPI FIFOs are accomplished through the use of the eDMA controller or
through Host software. See
for a conceptual diagram of the queue data transfer control in the
MPC5644A MCU.
Figure 30-53. DSPI queue transfer control in the MPC5644A
System RAM
DSPI
DMA Controller/Host
TX Queue
RX FIFO
TX FIFO
Shift Register
Data
Data
Address
RX Queue
Data
Data
Address
DMA
Control/
Host
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