NXP Semiconductors MPC5644A, Reference Manual, Page: 42 / 1735

Introduction
MPC5644A Microcontroller Reference Manual, Rev. 6
42 Freescale Semiconductor
— Hardware scheduler works as a “task management” unit, dispatching event service routines by
predefined, host-configured priority
— Automatic channel context switch when a “task switch” occurs, that is, one function thread
ends and another begins to service a request from other channel: channel-specific registers,
flags and parameter base address are automatically loaded for the next serviced channel
— SPRAM shared between host CPU and eTPU2, supporting communication either between
channels and host or inter-channel
— Hardware implementation of four semaphores support coherent parameter sharing between
both eTPU engines
— Dual-parameter coherency hardware support allows atomic access to two parameters by host
• Test and development support features:
— Nexus Class 1 debug, supporting single-step execution, arbitrary microinstruction execution,
hardware breakpoints and watchpoints on several conditions
— Software breakpoints
— SCM continuous signature-check built-in self test (MISC - multiple input signature calculator),
runs concurrently with eTPU2 normal operation
1.4.13 Reaction module
The reaction module provides the ability to modulate output signals to manage closed loop control without
CPU assistance. It works in conjunction with the eQADC and eTPU2 to increase system performance by
removing the CPU from the current control loop.
The reaction module has the following features:
• 6 reaction channels
• Each channel output is a bus of 3 signals, providing ability to control 3 inputs.
• Each channel can implement a peak and hold waveform, making it possible to implement up to six
independent peak and hold control channels
Target applications include solenoid control for direct injection systems and valve control in automatic
transmissions
1.4.14 eQADC
The enhanced queued analog to digital converter (eQADC) block provides accurate and fast conversions
for a wide range of applications. The eQADC provides a parallel interface to two on-chip analog to digital
converters (ADC), and a single master to single slave serial interface to an off-chip external device. Both
on-chip ADCs have access to all the analog channels.
The eQADC prioritizes and transfers commands from six command conversion command ‘queues’ to the
on-chip ADCs or to the external device. The block can also receive data from the on-chip ADCs or from
an off-chip external device into the six result queues, in parallel, independently of the command queues.
The six command queues are prioritized with Queue_0 having the highest priority and Queue_5 the lowest.
Queue_0 also has the added ability to bypass all buffering and queuing and abort a currently running