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Enhanced Queued Analog-to-Digital Converter (EQADC)
MPC5644A Microcontroller Reference Manual, Rev. 6
Freescale Semiconductor
1041
25.5.2.11
EQADC
CFIFO Status Snapshot Registers (
EQADC
_CFSSR)
The EQADC CFIFO Status Snapshot Registers (EQADC_CFSSR) contain status fields to track the
operation status of each CFIFO and the transfer counter of the last CFIFO to initiate a command transfer
to the internal/external CBuffers. EQADC_CFSSR0-1 are related to the on-chip CBuffers (CBuffer0-1)
while EQADC_CFSSR2 is related to the external CBuffers. All fields of a particular EQADC_CFSSR
register are captured at the beginning of a command transfer to the CBuffer associated with that register.
Note that captured status register values are associated with previous command transfer. This means that
the CFSSR registers capture the status registers before the status registers change because of the transfer
of the current command that is about to be popped from the CFIFO. The EQADC_CFSSR registers are
read only. Writing to the EQADC_CFSSR registers has no effect.
Figure 25-18.
EQADC
CFIFO Status Snapshot Register 0 (
EQADC
_CFSSR0)
Table 25-16.
EQADC
CFIFO Transfer Counter Register x (
EQADC
_CFTCRx) field description
Field
Description
TC_CFx
[0:10]
Transfer Counter for CFIFOx
TC_CFx counts the number of commands which have been completely transferred from
CFIFOx. The transfer of entries bound for the on-chip ADCs is considered completed when
they are stored in the appropriate CBuffer. The transfer of entries bound for an external
device is considered completed when the serial transmission of the entry is completed. The
EQADC increments the TC_CFx value by one after a command is transferred. TC_CFx
resets to zero after EQADC completes transferring a command with an asserted EOQ bit.
Writing any value to TC_CFx sets the counter to that written value.
Note:
If CFIFOx is in TRIGGERED state when its MODEx field is programmed to disabled,
the exact number of entries transferred from the CFIFO until that point - TC_CFx - is
only known after the CFIFO status changes to IDLE, as indicated by CFSx. For details
refer to
Section 25.6.4.6.1, Disabled Mode
.
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R
CFS0_TCB
0
CFS1_TCB
0
CFS2_TCB
0
CFS3_TCB
0
CFS4_TCB
0
CFS5_TCB
0
0
0
0
0
W
RESET:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
R
0
LCFTCB0
TC_LCFTCB0
W
RESET:
0
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Register address: EQA0x0A0
Summary of Contents for MPC5644A
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