NXP Semiconductors MPC5644A, Reference Manual, Page: 1202 / 1735

Decimation Filter
MPC5644A Microcontroller Reference Manual, Rev. 6
1202 Freescale Semiconductor
26.5 Functional description
26.5.1 Overview
Figure 26-1 shows the block diagram of the Decimation Filter. The Control Logic provides the control
signals for all other sub-modules. The PSI data interface is subdivided into two sub-modules, transmitter
and receiver, that are accessed by the PSI slave-bus interface. The bypass path is used when the filter is
disabled and the incoming data can be transmitted back to the master block without being processed by the
Filter algorithm. The Filter hardware is implemented in such a way that an IIR (1 x 4 poles) or FIR filter
type can be implemented. The selection between the two types of filter algorithms is implemented by the
Control Logic sub-block.
The Coefficient register file provides the digital filter coefficients. This block is a register bank with
read/write access by the device slave-bus interface. The Filter TAP registers are also accessed through the
device slave-bus line interface, providing additional debug capabilities to the Decimation Filter block. The
MAC (Multiply Accumulate) sub-block executes the filter arithmetic operations controlled by the Control
Logic. The MAC results are routed to the Filter TAP registers and to the output buffer when the result is a
decimated filter sample.
26.5.2 Parallel Side Interface (PSI) description
This section describes the operation of the Parallel Side Interface (PSI) sub-block which is responsible for
communication and data exchange between the master block (for instance, the eQADC block) and the
Decimation Filter block.
The decimation filter receives sample data from the master block. The input data bus format is presented
in
Figure 26-15 . The sample data arrives along with the control bits. These control bits are decoded and
the proper action is decided in the Control Logic sub-block. When the decimation filter finishes its
processing and a result is available, the read request signal is issued to the master block. This data transfer
request remains set until the result is read by the master block.
When using two or more decimation filter blocks in the device, the output of the second block is connected
to the input data of the next block, and the output of the first block is connected to the read data input of
the PSI master block.
26.5.3 Input buffer description
The decimation filter receives data samples for filtering from a master block (e.g., eQADC) using the PSI
interface, or from the CPU using the device slave-bus interface. The data source is selected by the ISEL
bit of the module configuration register DECFILTER_MCR.
When the device slave-bus interface is selected and DMA operation is chosen (DECFILTER_MCR bit
DSEL = 1), the input data request signal is asserted when the input buffer is empty. When DMA operation
is not chosen (DSEL = 0) in standalone or PSI output mixed modes, the logic asserts an input interrupt
request and the input buffer waits for data from the device slave-bus.
Input buffer filling is flagged by the DECFILTER_MSR bit IDF. The IDF flag remains set, even after the
input data has been consumed and the buffer is free, until it is cleared by software.