NXP Semiconductors MPC5644A, Reference Manual, Page: 346 / 1735

Interrupt Controller (INTC)
MPC5644A Microcontroller Reference Manual, Rev. 6
346 Freescale Semiconductor
NOTE
Since bits IVOR4[28:31] are not part of the offset value, the vector offset
must be located on a quad-word (16-byte) aligned location in memory.
In the software vector mode, the interrupt exception handler software must read the INTC interrupt
acknowledge register (INTC_IACKR) to obtain the vector number and base address of the handler
associated with the corresponding peripheral or software interrupt request. The INTC_IACKR register
contains a 21-bit or 20-bit address for a vector table base address (VTBA). The address is then used to
branch to the corresponding routine for that peripheral or software interrupt source.
Figure 15-5. Software Vector Mode: Interrupt Exception Handler Address Calculation
Reading the INTC_IACKR acknowledges the INTC’s interrupt request and negates the interrupt request
to the processor. The interrupt request to the processor does not clear if a higher priority interrupt request
arrives. Even in this case, INTVEC does not update to the higher priority request until the lower priority
interrupt request is acknowledged by reading the INTC_IACKR. The reading also pushes the PRI value
in the INTC current priority register (INTC_CPR) to the LIFO and updates PRI in the INTC_CPR with
the priority of the interrupt request. The INTC_CPR masks any peripheral or software configurable
interrupt request at the same or lower priority of the current value of the PRI field in INTC_CPR from
generating an interrupt request to the processor.
The interrupt exception handler must write to the end-of-interrupt register (INTC_EOIR) to complete the
operation (assuming the source of the interrupt has been cleared). Writing to the INTC_EOIR ends the
servicing of the interrupt request. The INTC’s LIFO is popped into the INTC_CPR's PRI field by writing
to the INTC_EOIR, and the size of a write does not affect the operation of the write. Those values and sizes
written to this register neither update the INTC_EOIR contents nor affect whether the LIFO pops. For
possible future compatibility, write four bytes of all 0s to the INTC_EOIR. The timing relationship
between popping the LIFO and disabling recognition of external input has no restriction. The writes can
happen in either order.
However, disabling recognition of the external input before popping the LIFO eases the calculation of the
maximum stack depth at the cost of postponing the servicing of the next interrupt request.
31 16 15 0
IVPR
31 28 27 16 15 0
+ IVOR4
31 28 27 16 15 0
0x00
0x00
OFFSET
OFFSET PREFIX
0x0000
PREFIX
= Interrupt exception
0x0000
handler address