NXP Semiconductors MPC5644A, Reference Manual, Page: 577 / 1735

Frequency-modulated phase locked loop (FMPLL)
MPC5644A Microcontroller Reference Manual, Rev. 6
Freescale Semiconductor 577
Figure 17-7. Clock quality monitor
17.5.4.1 Alternate/Backup clock selection
If loss-of-clock detection is enabled by LOCEN, the FMPLL is operating in normal mode and the Clock
Quality Monitor detects a failure at the FMPLL output clock, then a backup clock selection feature
automatically connects the system clock to the reference clock input (either external or crystal reference).
After this happens, the system clock remains connected to the reference clock until next system reset, even
if the FMPLL regains itself and relocks. If, however, the reference clock also fails, either simultaneously
or after the FMPLL failure, the system clock is connected back to the FMPLL output.
If the reference fails in normal mode, then no backup clock selection occurs, and the FMPLL output
continues to be the system clock. If the reference stops, the FMPLL will operate in free-running mode.
Table 17-12. Loss-of-clock monitoring
Operating mode LOCEN
1
1
LOCEN is the loss-of-clock enable bit in either FMPLL_SYNCR or FMPLL_ESYNCR2, depending on
FMPLL_ESYNCR1[EMODE].
Reference clock
monitored?
FMPLL output
monitored?
Bypass mode with external reference and PLL off — No No
Bypass mode with crystal reference and PLL off — Yes No
Bypass mode with external reference and PLL running — No No
Bypass mode with crystal reference and PLL running — Yes No
Normal mode with external reference 0 No No
1 No Yes
Normal mode with crystal reference 0 No No
1 Yes Yes
RC oscillator
4 MHz
Crystal oscillator
4 – 40 MHz
> 1.5 MHz
Counter 1
Counter 2
Counter 3
PLL
Control
Logic