NXP Semiconductors MPC5644A, Reference Manual, Page: 571 / 1735

Frequency-modulated phase locked loop (FMPLL)
MPC5644A Microcontroller Reference Manual, Rev. 6
Freescale Semiconductor 571
17.4.2.4 Enhanced Synthesizer Control Register 2 (ESYNCR2)
16–24 Reserved, should be cleared.
25–31
EMFD Enhanced multiplication factor divider
This 7-bit field controls the value of the divider in the FMPLL feedback loop. The value specified by the
EMFD bits establishes the multiplication factor applied to the reference frequency. The valid range of
multiplication factors is 32 (010_0000) to 96 (110_0000). Values outside this range are invalid and will
cause the FMPLL to produce unpredictable clock output.
00x_xxxx
Invalid
010_0000 Divide by 32
010_0001 Divide by 33
...
101_1111
Divide by 95
110_0000 Divide by 96
110_0001 Invalid
...
111_1111
Invalid
Offset 0x000C Access: User read/write
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R 0 0 0 0 0 0 0 0
LO
C
E
N
LOLRE
L
O
CRE
LOL
IR
Q
LOCIRQ
0 0 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ERFD
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1
Figure 17-5. Enhanced Synthesizer Control Register 2 (ESYNCR2)
Table 17-9. ESYNCR2 field descriptions
Field Description
0–7 Reserved, should be cleared.
8
LOCEN
Loss-of-clock enable
The LOCEN bit determines if the loss-of-clock function is operational. This bit only has effect in normal
mode. In bypass mode, the loss-of-clock function is always enabled, regardless of the state of the LOCEN
bit. Furthermore, the LOCEN bit has no effect on the loss-of-lock detection circuitry.
0 Loss of clock disabled
1 Loss of clock enabled
Table 17-8. ESYNCR1 field descriptions (continued)
Field Description