NXP Semiconductors MPC5644A, Reference Manual, Page: 1279 / 1735

Deserial Serial Peripheral Interface (DSPI)
MPC5644A Microcontroller Reference Manual, Rev. 6
Freescale Semiconductor 1279
Table 30-19. DSPI_DSICR field description
Field Description
0
MTOE
Multiple Transfer Operation Enable
The MTOE bit enables multiple DSPIs to be connected in a parallel or serial configuration. See
Section 30.9.3.6, Multiple transfer operation (MTO) , for more information.
0 Multiple Transfer Operation disabled
1 Multiple Transfer Operation enabled
The MTOE and TSB bits should not be set simultaneously.
1 MSB of the Frame Size
If the bit is set, 16 is added to the frame size, defined by field DSPI_CTARn[FMSZ]. DSPI_CTARn
register is selected by field DSPI_DSICR[DSICTAS].
2–7
MTOCNT[0:5]
Multiple Transfer Operation Count
The MTOCNT field selects number of bits to be shifted out during a transfer in Multiple Transfer
Operation. The field sets the number of SCK cycles that the bus master will generate to complete the
transfer. The number of SCK cycles used will be one more than the value in the MTOCNT field. The
number of SCK cycles defined by MTOCNT must be equal to or greater than the frame size. When
TSBC is set, MTOCNT field has no effect.
8–10 Reserved, should be cleared.
11
TSBC
Timed Serial Bus Configuration
The TSBC bit enables the Timed Serial Bus Configuration. This configuration allows 32-bit data to be
used. It also allows t
DT
to be programmable. See Section 30.9.8, Timed serial bus (TSB) ” for detailed
information.
0 Timed Serial Bus Configuration disabled
1 Timed Serial Bus Configuration enabled
If this bit is clear the DSPI_DSICR1 register value has no effect.
12
TXSS
Transmit Data Source Select
The TXSS bit selects the source of data to be serialized. The source can be either data from host
Software written to the DSPI DSI Alternate Serialization Data Register (DSPI_ASDR), or Parallel
Input pin states latched into the DSPI DSI Serialization Data Register (DSPI_SDR).
0 Source of serialized data is the DSPI_SDR
1 Source of serialized data is the DSPI_ASDR
13
TPOL
Trigger Polarity
The TPOL bit selects the active edge of the hardware trigger input signal (HT). initiating DSI frames
transfer. See
Section 30.9.3.5, DSI transfer initiation control , for more information.
0 Falling edge will initiate a transfer
1 Rising edge will initiate a transfer
14
TRRE
Trigger Reception Enable
The TRRE bit enables the DSPI to initiate DSI frames transfer with external trigger signal. See
Section 30.9.3.5, DSI transfer initiation control , for more information.
0 Trigger signal reception disabled
1 Trigger signal reception enabled
15
CID
Change In Data Transfer Enable
The CID bit enables a change in serialization data to initiate DSI frames transfer. in DSI and CSI
configurations. When the CID bit is set, DSI frames are initiated when the current DSI data differs
from the previous DSI data shifted out. Refer to
Section 30.9.3.5, DSI transfer initiation control , for
more information.