NXP Semiconductors MPC5644A, Reference Manual, Page: 41 / 1735

Introduction
MPC5644A Microcontroller Reference Manual, Rev. 6
Freescale Semiconductor 41
• Channels support unordered transitions: transition 2 can now be detected before transition 1.
Related to this enhancement, the transition detection latches (TDL1 and TDL2) can now be
independently negated by microcode.
• A new User Programmable Channel Mode has been added: the blocking, enabling, service request
and capture characteristics of this channel mode can be programmed via microcode.
• Microinstructions now provide an option to issue Interrupt and Data Transfer requests selected by
channel. They can also be requested simultaneously at the same instruction.
• Channel Flags 0 and 1 can now be tested for branching, in addition to selecting the entry point.
• Channel digital filters can be bypassed.
The eTPU2 includes these distinctive features:
• 32 channels; each channel associated with one input and one output signal
— Enhanced input digital filters on the input pins for improved noise immunity
— Identical, orthogonal channels: each channel can perform any time function. Each time
function can be assigned to more than one channel at a given time, so each signal can have any
functionality.
— Each channel has an event mechanism which supports single and double action functionality
in various combinations. It includes two 24-bit capture registers, two 24-bit match registers,
24-bit greater-equal and equal-only comparators.
— Input and output signal states visible from the host
• 2 independent 24-bit time bases for channel synchronization:
— First time base clocked by system clock with programmable prescale division from 2 to 512 (in
steps of 2), or by output of second time base prescaler
— Second time base counter can work as a continuous angle counter, enabling angle based
applications to match angle instead of time
— Both time bases can be exported to the eMIOS timer module
— Both time bases visible from the host
• Event-triggered microengine:
— Fixed-length instruction execution in two-system-clock microcycle
— 14 KB of code memory (SCM)
— 3 KB of parameter (data) RAM (SPRAM)
— Parallel execution of data memory, ALU, channel control and flow control sub-instructions in
selected combinations
— 32-bit microengine registers and 24-bit wide ALU, with 1 microcycle addition and subtraction,
absolute value, bitwise logical operations on 24-bit, 16-bit, or byte operands, single-bit
manipulation, shift operations, sign extension and conditional execution
— Additional 24-bit Multiply/MAC/Divide unit which supports all signed/unsigned
Multiply/MAC combinations, and unsigned 24-bit divide. The MAC/Divide unit works in
parallel with the regular microcode commands.
• Resource sharing features support channel use of common channel registers, memory and
microengine time: