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Enhanced Queued Analog-to-Digital Converter (EQADC)
MPC5644A Microcontroller Reference Manual, Rev. 6
Freescale Semiconductor
1077
Table 25-50. Conversion Command Format for the Standard Configuration field description
Field
Description
0
EOQ
End Of Queue Bit
The EOQ bit is asserted in the last command of a CQueue to indicate to the EQADC that a
scan of the CQueue is completed. EOQ instructs the EQADC to reset its current CFIFO
transfer counter value (TC_CF) to zero. Depending on the CFIFO mode of operation, the
CFIFO status will also change upon the detection of an asserted EOQ bit on the last
transferred command - see
Section 25.6.4.6, CFIFO Scan Trigger Modes
, for details.
1 Last entry of the CQueue.
0 Not the last entry of the CQueue.
Note:
If both the PAUSE and EOQ bits are asserted in the same command message the
respective flags are set, but the CFIFO status changes as if only the EOQ bit were
asserted.
1
PAUSE
Pause Bit
The Pause bit allows software to create sub-queues within a CQueue. When the EQADC
completes the transfer of a command with an asserted Pause bit, the CFIFO enters the
WAITING FOR TRIGGER state. Refer to
Section 25.6.4.7.1, CFIFO Operation Status
, for a
description of the state transitions. The Pause bit is only valid when CFIFO operation mode
is configured to single or continuous-scan edge trigger mode.
1 Enter WAITING FOR TRIGGER state after transfer of the current Command Message.
0 Do not enter WAITING FOR TRIGGER state after transfer of the current Command
Message.
Note:
If both the PAUSE and EOQ bits are asserted in the same command message the
respective flags are set, but the CFIFO status changes as if only the EOQ bit were
asserted.
2
REP
Repeat/loop Start Point Indication Bit
The REP bit is asserted in the command to indicate where is the start point of the sub-queue
to be repeated when the streaming mode is enabled. The PAUSE bit indicates the end point
of the sub-queue. Therefore, both can occur in the same command or in separated ones. If
two or more REP bits are read before a PAUSE bit, this is an error case and the intermediary
REP bits are ignored.
1 Indicates the start point of the sub-queue to be repeated.
0 It is not the start point of a loop.
5
EB
External Buffer Bit
A negated EB bit indicates that the command is sent to an internal CBuffer.
Command is sent to an internal buffer.
6
BN
Buffer Number Bit
BN indicates which buffer the message will be stored in. Buffers 1 and 0 can either internal
or external depending on the EB bit setting.
Message stored in buffer 1.
Message stored in buffer 0.
7
CAL
CALibration Bit
CAL indicates if the returning conversion result must be calibrated.
Calibrate conversion result.
Do not calibrate conversion result.
Summary of Contents for MPC5644A
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