NXP Semiconductors MPC5644A, Reference Manual, Page: 150 / 1735

Enhanced Direct Memory Access Controller (eDMA)
MPC5644A Microcontroller Reference Manual, Rev. 6
150 Freescale Semiconductor
conditions except scatter-gather and minor loop link error are reported as the channel is activated and
assert an error interrupt request if enabled. When properly enabled, a scatter-gather configuration error is
reported when the scatter-gather operation begins at major loop completion. A minor loop channel link
configuration error is reported when the link operation is serviced at minor loop completion.
If a system bus read or write is terminated with an error, the data transfer is immediately stopped and the
appropriate bus error flag is set. In this case, the state of the channel’s transfer control descriptor is updated
by the DMA engine with the current source address, destination address, and minor loop byte count at the
point of the fault. If a bus error occurs on the last read prior to beginning the write sequence, the write is
executed using the data captured during the bus error. If a bus error occurs on the last write prior to
switching to the next read sequence, the read sequence is executed before the channel is terminated due to
the destination bus error.
A transfer may be cancelled by software via the bit EDMA_CR[CX]. When a cancel transfer request is
recognized, the eDMA engine stops processing the channel. The current read-write sequence is allowed to
finish. If the cancel occurs on the last read-write sequence of a major or minor loop, the cancel request is
discarded and the channel retires normally.
The error cancel transfer is the same as a cancel transfer except the DMAES register is updated with the
cancelled channel number and error cancel bit is set. The TCD of a cancelled channel has the source
address and destination address of the last transfer saved in the TCD. It is the responsibility of the user to
initialize the TCD again should the channel need to be restarted because the aforementioned fields have
been modified by the eDMA engine and no longer represent the original parameters. When a transfer is
cancelled via the error cancel transfer mechanism (setting EDMA_CR[ECX]), the channel number is
loaded into field EDMA_ESR[ERRCHN] and the bits EDMA_ESR[ECX] and EDMA_ESR[VLD] are
set. In addition, an error interrupt may be generated if enabled. Refer to
Section 8.3.2.14, eDMA Error
Registers (EDMA_ERH, EDMA_ERL) .
The occurrence of any type of error causes the DMA engine to stop the active channel and the appropriate
channel bit in the eDMA error register to be asserted. At the same time, the details of the error condition
are loaded into the EDMA_ESR. The major loop complete indicators, setting the transfer control
descriptor DONE flag and the possible assertion of an interrupt request, are not
affected when an error is
detected. After the error status has been updated, the DMA engine continues to operate by servicing the
next appropriate channel. A channel that experiences an error condition is not automatically disabled. If a
channel is terminated by an error and then issues another service request before the error is fixed, that
channel will execute and terminate with the same error condition.