NXP Semiconductors MPC5644A, Reference Manual, Page: 285 / 1735

External Bus Interface (EBI)
MPC5644A Microcontroller Reference Manual, Rev. 6
Freescale Semiconductor 285
14.4.1 Register Descriptions
NOTE
Other than the exceptions noted below, EBI registers must not be written
while a transaction to the EBI (from internal master) is in progress (or within
2 CLKOUT cycles after a transaction has just completed, to allow internal
state machines to go IDLE). In those cases, the behavior is undefined.
Exceptions that can be written while an EBI transaction is in progress:
- All bits in EBI_TESR
See Section 14.6.1, Booting from external memory for related application
information.
E0x8 EBI Transfer Error Status Register (EBI_TESR)
E0xC EBI Bus Monitor Control Register (EBI_BMCR)
E0x10 EBI Base Register Bank 0 (EBI_BR0)
E0x14 EBI Option Register Bank 0 (EBI_OR0)
E0x18 EBI Base Register Bank 1 (EBI_BR1)
E0x1C EBI Option Register Bank 1 (EBI_OR1)
E0x20 EBI Base Register Bank 2 (EBI_BR2)
E0x24 EBI Option Register Bank 2 (EBI_OR2)
E0x28 EBI Base Register Bank 3 (EBI_BR3)
E0x2C EBI Option Register Bank 3 (EBI_OR3)
E0x30 –
E0x3C
Reserved
E0x40 EBI Calibration Base Register Bank 0 (EBI_CAL_BR0)
E0x44 EBI Calibration Option Register Bank 0 (EBI_CAL_OR0)
E0x48 EBI Calibration Base Register Bank 1 (EBI_CAL_BR1)
E0x4C EBI Calibration Option Register Bank 1 (EBI_CAL_OR1)
E0x50 EBI Calibration Base Register Bank 2 (EBI_CAL_BR2)
E0x54 EBI Calibration Option Register Bank 2 (EBI_CAL_OR2)
E0x58 EBI Calibration Base Register Bank 3 (EBI_CAL_BR3)
E0x5C EBI Calibration Option Register Bank 3 (EBI_CAL_OR3)
Table 14-4. EBI Address Map (continued)
Address Use