NXP Semiconductors MPC5644A, Reference Manual, Page: 1523 / 1735

FlexRay Communication Controller (FlexRay)
MPC5644A Microcontroller Reference Manual, Rev. 6
Freescale Semiconductor 1523
33.5.2.71 ECC Error Report and Injection Control Register (FR_EERICR)
This register configures the error injection and error reporting and provides the selector for the content of
the report registers.
LRNE_IE LRAM Non-Corrected Error Interrupt Enable — This flag controls if the LRAM Non-Corrected Error
Interrupt line is asserted when the LRNE_IF flag is set.
0 Disable interrupt line
1 Enable interrupt line
LRCE_IE LRAM Corrected Error Interrupt Enable — This flag controls if the LRAM Corrected Error Interrupt
line is asserted when the LRCE_IF flag is set.
0 Disable interrupt line
1 Enable interrupt line
DRNE_IE DRAM Non-Corrected Error Interrupt Enable — This flag controls if the DRAM Non-Corrected Error
Interrupt line is asserted when the DRNE_IF flag is set.
0 Disable interrupt line
1 Enable interrupt line
DRCE_IE DRAM Corrected Error Interrupt Enable — This flag controls if the DRAM Corrected Error Interrupt
line is asserted when the DRCE_IF flag is set.
0 Disable interrupt line
1 Enable interrupt line
Base + 0x00F2 Write: ERS: Anytime
ERM, EIM, EIE: IDL
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R BSY 0 0 0 0 0
ERS
0 0 0
ERM
0 0
EIM EIE
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 33-102. ECC Error Report and Injection Control Register (FR_EERICR)
Table 33-81. FR_EERICR field description
Field Description
BSY Register Update Busy — This field indicates the current state of the ECC configuration update and
controls the register write access condition IDL specified in “ Section 33.5.2.2, Register write access ”
0 ECC configuration is idle
1 ECC configuration is running
ERS Error Report Select — This field selects the content of the ECC Error reporting registers.
00 show PE DRAM non-corrected error information
01 show PE DRAM corrected error information
10 show CHI LRAM non-corrected error information
11 show CHI LRAM corrected error information
ERM Error Report Mode — This bit configures the type of data written into the internal error report registers
on the detection of a memory error.
0 store data and code as delivered by ECC decoding logic.
1 store data and code as read from the memory.
Table 33-80. FR_EEIFER field description
Field Description