NXP Semiconductors MPC5644A, Reference Manual, Page: 710 / 1735

Reaction Module (REACM)
MPC5644A Microcontroller Reference Manual, Rev. 6
710 Freescale Semiconductor
23.3.10 REACM Shared Timer Bank Registers (REACM_STBK)
The REACM Shared Timer Bank Registers (REACM_STBK) is a set of registers which define the values
used by the Reaction Module Timer. The timer values are programmed by the host CPU during the
configuration of the Reaction Module. Modulation Word accessed by the reaction channel contains the
address of a specific Timer value stored in the Shared Timer bank. By selecting a Timer value the reaction
channel also selects and enables a counter. When this counter reaches the selected Timer value a timeout
indication is generated for the reaction channel that initiated the counter. This event is used, for example,
to indicate that a next Modulation Word should be used for the modulation.
Figure 23-12. REACM Shared Timer Bank Registers (REACM_STBK)
23.3.11 REACM Hold-off Timer Bank Registers (REACM_HOTBK)
The REACM Hold-off Timer Bank Registers (REACM_HOTBK) is a set of registers that defines the
values used by the reaction channels to measure hold-off time on certain modulation schemes. The timer
values are programmed by software and addressed by the reaction channel based on the data read from a
Modulation Word.
0b1100 to 0b1111 Reserved
Address: REACM_BASE (0xC3FC_7000) + (from 0x0300 to 0x0308) Access: User read/write
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
SHARED_TIMER[15:0]
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Table 23-14. REACM_STBK field descriptions
Field Description
0–15 Reserved, should be cleared.
16–31
SHARED_TIMER
[15:0]
Timer Value
The SHARED_TIMER[15:0] value is one element of the Timer Register Bank. Up to three timer
values can be stored within the Timer Bank.
Note: When using the shared timer for sequence advance, the counted time (considering
prescaler) must be greater than 64 clock cycles.
Table 23-13. REACM_CHRRn[CHIR] values (continued)
CHIR[3:0] eTPU A channel