NXP Semiconductors MPC5644A, Reference Manual, Page: 777 / 1735

Enhanced Time Processing Unit (eTPU2)
MPC5644A Microcontroller Reference Manual, Rev. 6
Freescale Semiconductor 777
1 MDIS—Module Disable Bit
When MDIS is set, the engine shuts down its internal clocks, going into Module Disable Mode. TCR1 and
TCR2 cease to increment, and input sampling stops. The engine asserts the stop flag (STF) bit to indicate
that it has stopped However, the BIU continues to run, and the Host can access all registers except for the
channel registers (see list of channel registers on
Section 24.4.7, Channel configuration and control
registers ). After MDIS is set, even before STF asserts, data read from the channel registers is not
meaningful and writes are ineffective, issuing a Bus Error. When the MDIS bit is asserted while the
microcode is executing, the eTPU will stop when the thread is complete.
1: Commands engine to stop its clocks.
0: eTPU engine runs.
Stop completes on the next system clock after the stop condition is valid. The MDIS bit is write-protected
when VIS = 1.
Note: The Timebase registers can still be read with MDIS = 1, but writes are ineffective and a Bus Error is
issued.
Global Channel Registers and SPRAM can be accessed normally.
Note: Once MDIS is switched from 1 to 0 or vice versa, it must not be written a different value until STF
changes accordingly.
2 Reserved
3 STF—Stop Flag Bit
The eTPU system is fully stopped after the eTPU engine asserts its stop flag (STF). In case of an IP-Bus
stop, the eTPU acknowledges the stop only after any ongoing thread is complete and the eTPU engine
has stopped.
1: Engine has stopped (after the local MDIS bit has been asserted, or after the IP-Bus stop line has been
asserted).
0: Engine is operating.
Summarizing engine stop conditions, which STF reflects:
STF_1:= (after stop completed) MDIS_1 | device stop request
STF_2:= (after stop completed) MDIS_2 | device stop request
STF_1 and STF_2 mean STF bit from engine 1 and STF bit from engine 2 respectively.
4-7 Reserved
8 HLTF—Halt Mode Flag
If eTPU engine entered halt state, this flag is asserted. The flag remains asserted while the microengine
is in halt state, even during a single-step or forced instruction execution. See
Section 24.5.10.2,
Development support features , for further details about entering Halt Mode.
1: eTPU engine is halted
0: eTPU engine is not halted.
9-11 Reserved
Table 24-9. ETPU_ECR field description
Field Description