NXP Semiconductors MPC5644A, Reference Manual, Page: 1403 / 1735

FlexCAN Module
MPC5644A Microcontroller Reference Manual, Rev. 6
Freescale Semiconductor 1403
32.4.5 Register descriptions
The FlexCAN registers are described in this section in ascending address order.
32.4.5.1 Module Configuration Register (MCR)
This register defines global system configurations, such as the module operation mode (e.g., low power)
and maximum message buffer configuration. Most of the fields in this register can be accessed at any time,
except the MAXMB field, which should only be changed while the module is in Freeze Mode.
Figure 32-7. Module Configuration Register (MCR)
Base + 0x0000
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R
MDIS FRZ FEN HALT
N
O
T
RDY
W
AK_MSK
SO
FTRST
FR
Z
A
C
K
SUPV
SLF_WAK
WRNEN
MDISACK
WAK_SRC
0
SRXDIS
MB
FEN
W
RESET: 0 1 0 1 1 0 0 1 1 0 0 0 0 0 0 0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R 0 0
LPRIO_EN
AEN
0 0
IDAM
0 0
MAXMB
W
RESET: 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1
= Unimplemented or Reserved
Table 32-8. Module Configuration Register (MCR) field descriptions
Field Description
MDIS Module Disable
This bit controls whether FlexCAN is enabled or not. When disabled, FlexCAN shuts down the
clocks to the CAN Protocol Interface and Message Buffer Management submodules. This is the
only bit in MCR not affected by soft reset. See
Section 32.5.9.2, Module Disable Mode for more
information.
1: Disable the FlexCAN module
0: Enable the FlexCAN module
FRZ Freeze Enable
The FRZ bit specifies the FlexCAN behavior when MCR[HALT] is set or when Debug Mode is
requested at MCU level. When FRZ is asserted, FlexCAN is enabled to enter Freeze Mode.
Negation of this bit field causes FlexCAN to exit from Freeze Mode.
1: Enabled to enter Freeze Mode
0: Not enabled to enter Freeze Mode