NXP Semiconductors MPC5644A, Reference Manual, Page: 837 / 1735

Enhanced Time Processing Unit (eTPU2)
MPC5644A Microcontroller Reference Manual, Rev. 6
Freescale Semiconductor 837
In order to ensure coherent access to a group of parameters by two or more contenders, each contender
must have atomic access to the shared parameters. Atomicity conditions are discussed in
Section 24.5.4.1, Host Side Atomic Access , and Section 24.5.4.2, Microengine Side Atomic Accesses .
24.5.4.1 Host Side Atomic Access
Host side atomic accesses can be achieved by either of following ways:
• For one parameter, the SPRAM should be accessed by 32-bit-wide data transfers to ensure
coherency
• For two parameters only, using the Coherent Dual-Parameter Controller.
indirectly, for any number of parameters, by requesting microcode to coherently access SPRAM in its
behalf. The host side atomicity problem becomes, then, a microengine side atomicity problem. Some
methods that use this approach to achieve coherency are described in
Section 24.6.3, Multiple parameter
coherency methods .
24.5.4.2 Microengine Side Atomic Accesses
24.5.4.2.1 Microengine single-parameter atomicity
SPRAM should be accessed by 32-bit-wide data transfers to ensure atomicity for 32-bit parameters. This
applies either to Host-Microengine coherency or Microengine-Microengine coherency in a dual eTPU
engine system.
24.5.4.2.2 Microengine dual-parameter atomicity
Microengine has the ability to access two parameters coherently in back-to-back accesses, at random
addresses: once it accesses SPRAM, it has priority over Host for another access in the next microcycle (see
Section 24.5.4.5, SPRAM Arbitration ). Note that it applies only to Microengine-Host coherency . For
Microengine-Microengine coherency in a dual eTPU engine system, one must use Hardware Semaphores
(see
Section 24.5.4.4, Hardware Semaphores ).
Microengine dual back-to-back accesses are guaranteed to be atomic in relation to Host slave accesses or
Coherent Dual-parameter Controller, regardless of semaphore usage: Host or CDC accesses cannot
break-up a back-to-back Microengine access, neither Microengine can break a CDC transfer, due to the
SPRAM arbitration mechanism described in
Section 24.5.4.5, SPRAM Arbitration .
Atomicity is not guaranteed if microengine enters halt state in the middle of a back-to-back access (see
Section 24.5.10.2.2, Microengine halt state ): Host can access SPRAM while microengine is halted in the
middle of a back-to-back access.
24.5.4.2.3 Microengine Side Multiple Atomicity
Hardware Semaphores must be used for Microengine-Microengine coherency (more than 1 parameter)
since two or more accesses from one Microengine are not atomic with respect to the other.
For multiple Microengine-Host coherency, the software methods described in Section 24.6.3, Multiple
parameter coherency methods , or similar ones, must be used. Some of these methods rely on the fact that