NXP Semiconductors MPC5644A, Reference Manual, Page: 889 / 1735

Enhanced Time Processing Unit (eTPU2)
MPC5644A Microcontroller Reference Manual, Rev. 6
Freescale Semiconductor 889
The TCR2 bus runs through all the local engine channels. It transitions on clock T2 (see Section 24.7.1,
Microcycle and I/O timing ). In channels which select TCR2 as MatchA and/or MatchB source, TCR2
value is compared against MatchA and/or MatchB registers. A recognized match event sets its related
Match Recognition Latch 1 or 2, and according to the Predefined Channel Modes (PDCM) it may generate
a channel service request. For details on eTPU channels refer to
Section 24.5.5, Enhanced Channels .
The TCR2 counter is accessible by the microcode for read and write operations. Its current value is used
for getting the current counter value (representing signal transitions, time or angle), and the captured
values are used for channel relative count calculations of future events. The TCR2 value is readable to the
host through the ETPU_TB2R (refer to
Section 24.4.3.3, ETPU_TB2R – eTPU Time Base 2 (TCR2)
Visibility Register ). When the TCR2 bus value is imported from the STAC bus (STAC client mode), TCR2
is not writable by the microcode, and read access from the microcode or from the host reflect the imported
TCR2 value.
24.5.6.2.1 TCR2 clock prescaling
Except in Angle Mode, any clock source selected by TCR2CTL is prescaled by a factor of 1 to 64, selected
by ETPU_TBCR field TCR2P. For more information on prescaler configuration refer to
Section 24.4.3.1,
ETPU_TBCR – eTPU Time Base Configuration Register . The TCR2 Prescaler resets when etpu_gtbe_in
is negated. After reset, it starts counting up to TCR2P when etpu_gtbe_in is asserted. When TCR2
increments (etpu_gtbe_in = 1), the prescaler starts a new count and the new TCR2P becomes effective.
When TCR2 is written by microcode, the prescaler is reloaded with TCR2P and it becomes effective, if
etpu_gtbe_in is asserted.
The counter that divides the system clock by 8 before the prescaler also resets when etpu_gtbe_in is
negated, or when TCR2 is written by microcode.
24.5.6.2.2 TCR2 gated mode
TCR2 Gated mode is selected in field TCR2CTL of register ETPU_TBCR. In this mode the TCRCLK
signal enables or disables transfer of the system clock divided by 8 to the TCR2 prescaler. By
programming the prescaler, TCR2 can run at rates from system clock divided by eight down to system
clock divided by 512, in steps of eight system clock divisions. For more information refer to
Section 24.4.3.1, ETPU_TBCR – eTPU Time Base Configuration Register .
24.5.6.2.3 TCR2 signal transition modes
These modes are selected when the TCR2CTL field in ETPU_TBCR is set to rise, fall or “rise-and-fall”.
In these modes the TCRCLK signal is the TCR2 clock source, and its maximum transition rate depends
on the TCRCLK digital filter mode of operation. The TCRCLK digital filter can be programmed to use
the system clock divided by two, or use the same filter clock of the channels, controlled by the TCRCF
field in ETPU_TBCR. It contains an up-down counter which operates as a digital integrator, optimizing
signal latency in the selected mode and clock rate.
When system clock divided by two is selected, the synchronizer and the digital filter are guaranteed to pass
pulses that are wider than four system clocks (two filter clocks). Otherwise the TCRCLK is filtered with
the same filter clock as the channel input signals. For details on TCRCLK and channels digital filter