Enhanced Time Processing Unit (eTPU2)
MPC5644A Microcontroller Reference Manual, Rev. 6
Freescale Semiconductor
781
24.4.3
Time base registers
Each eTPU2 engine has two internally-generated time bases—Time Counter Registers—TCR1 and TCR2.
They provide 24-bit time bases, shared by all 32 channels of their associated eTPU2 engine. The registers
in the following sections control the configuration and visibility of the time bases. There is one of each of
these registers for each eTPU engine.
NOTE
Writes to this register issue bus error and are ineffective when MDIS = 1.
Reads are always allowed.
24.4.3.1
ETPU_TBCR – eTPU Time Base Configuration Register
This register configures several timebase options.
Figure 24-6. ETPU_TBCR Register
Offset: eTPU_A: eTP 0x020 eTPU_B: eTP 0x040
Access: User read/write
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R
TCR2CTL
TCRCF
AM
0
0
0
TCR2P
W
Reset
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
R
TCR1CTL
TCR
1
CS
0
0
0
0
0
TCR1P
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
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