NXP Semiconductors MPC5644A, Reference Manual, Page: 982 / 1735

Enhanced Time Processing Unit (eTPU2)
MPC5644A Microcontroller Reference Manual, Rev. 6
982 Freescale Semiconductor
A four-clock NOP occurs after each channel is serviced since there is one channel in each priority
level, i.e., a new cycle for a priority level is started after each channel is serviced. Time-slot
transitions occur after each time slot.
83 clocks * 25 ns/clock = 2075 ns
Conclusion: in this system configuration PWM can run with a minimum high time or low time of
2075 ns.
Note that in double match eTPU system the PWM can be serviced once in each period, and there
is no latency for minimum high time. The latency in eTPU PWM function will represent the
minimum PWM period.
Finding the WCL for PPWA on channel 1
The following shows how to find the WCL for PPWA on channel 1.
1. Find the worst-case service time for each active channel. See step 1 of previous example.
2. Assume channel 1 has just been serviced and that channels 0 and 2 are continuously requesting
service. Using the H-M-H-L-H-M-H time-slot sequence, map the channels that are granted for
each time slot. See
Figure 24-70 .
Figure 24-70. Next servicing for channel 1
Channel 0 will be serviced twice and channel 2 once before channel 1 is serviced again.
3. Add time for the six-clock CPU time-slot transitions. See Figure 24-70 and Table 24-123 .
Table 24-122. Worst-case latency for channel 0
Channel 0 worst-case service time 25 clocks
Channel 1 worst-case service time 46 clocks
Two 6-clock time-slot transitions 12 clocks
Total clocks 83 clocks
Table 24-123. Worst-case latency for channel 1
Two Channel 0 worst-case service times 50 clocks
Channel 1 worst-case service time 46 clocks
Channel 2 worst-case service time 11 clocks
TPU CH1 WCL TIM TPU CH1 WCL TIM
CHANNEL
SERVICED
WORST CASE LATENCY
CHANNEL 1
H M H L H M H H
CHANNEL 0
SERVICED
CHANNEL 2
SERVICED
= 10-CYCLE TIME SLOT TRANSITION
= 4-CYCLE NOP INSTRUCTION
CHANNEL 0
SERVICED
CHANNEL 1
SERVICED