NXP Semiconductors MPC5644A, Reference Manual, Page: 124 / 1735

Device Performance Optimization
MPC5644A Microcontroller Reference Manual, Rev. 6
124 Freescale Semiconductor
Refer to the e200z4 Power Architecture® Core Reference Manual for further details of MMU
configuration registers.
6.4 Application software
6.4.1 Compiler optimizations
The most significant opportunity for influencing the performance of a given application is by compiler and
linker optimizations. Optimizing is a trade off between code size and performance. Typically higher
performance of the application comes at the expense of larger code size. Compilers use a host of features,
such as loop unrolling, function inlining, and application profile feedback to make the desired trade-offs
between enhanced performance and minimized code size.
The data in Figure 6-4 shows the effects of compiler optimization on a simple application. In this case, the
Dhrystone benchmark was run under three conditions:
• Optimized for small code size
• Optimized for high performance
• A trade-off between code size and performance
Although this is an extreme example, it highlights how significant the role of the compiler and linker is in
determining the overall performance of an application.
VLE VLE
0: This page is a standard BookE page
1: This page is a VLE page
W Write-through required
I Cache inhibited
0: This page is considered cacheable
1: This page is considered cache-inhibited
M Memory coherence required
G Guarded
E Endianness
Table 6-3. MAS2 field descriptions (continued)
Field Description