
e200z4 Core
MPC5644A Microcontroller Reference Manual, Rev. 6
Freescale Semiconductor
133
Count-Leading-Zeros unit (CLZ), a 32x32 Hardware Multiplier array, and result feed-forward hardware.
Integer EU1 also supports hardware division.
Most arithmetic and logical operations are executed in a single cycle with the exception of multiply, which
is implemented with a 2-cycle pipelined hardware array, and the divide instructions. A
Count-Leading-Zeros unit operates in a single clock cycle.
The Instruction Unit contains a PC incrementer and dedicated Branch Address adders to minimize delays
during change of flow operations. Sequential prefetching is performed to ensure a supply of instructions
into the execution pipeline. Branch target prefetching using the BTB is performed to accelerate taken
branches. Prefetched instructions are placed into an 8-entry instruction buffer, with each entry capable of
holding a single 32-bit instruction or a pair of 16-bit instructions.
Branch target addresses are calculated in parallel with branch instruction decode. Conditional branches,
which are not taken execute in a single clock. Branches with successful BTB target prefetching have an
effective execution time of one clock if correctly predicted.
Memory load and store operations are provided for byte, halfword, word (32-bit), and doubleword data
with automatic zero or sign extension of byte and halfword load data as well as optional byte reversal of
data. These instructions can be pipelined to allow effective single cycle throughput. Load and store
multiple word instructions allow low overhead context save and restore operations. The load/store unit
contains a dedicated effective address adder to allow effective address generation to be optimized. There
is a single load-to-use bubble for load instructions.
The Condition Register unit supports the condition register (CR) and condition register operations defined
by the Power Architecture technology. The condition register consists of eight 4-bit fields that reflect the
results of certain operations, such as move, integer and floating-point compare, arithmetic, and logical
instructions, and provides a mechanism for testing and branching.
Vectored and autovectored interrupts are supported by the CPU. Vectored interrupt support is provided to
allow multiple interrupt sources to have unique interrupt handlers invoked with no software overhead.
The SPE APU supports vector instructions operating on 16 and 32-bit fixed-point data types, as well as
32-bit IEEE-754 single-precision floating-point formats, and supports single-precision floating-point
operations in a pipelined fashion. The 64-bit general purpose register file is used for source and destination
operands, and there is a unified storage model for single-precision floating-point data types of 32-bits and
the normal integer type. Low latency fixed-point and floating-point add, subtract, multiply, multiply-add,
multiply-sub, divide, compare, and conversion operations are provided, and most operations can be
pipelined.
Summary of Contents for MPC5644A
Page 2: ...MPC5644A Microcontroller Reference Manual Rev 6 2 Freescale Semiconductor...
Page 24: ...MPC5644A Microcontroller Reference Manual Rev 6 24 Freescale Semiconductor...
Page 26: ...MPC5644A Microcontroller Reference Manual Rev 6 26 Freescale Semiconductor...
Page 52: ...Introduction MPC5644A Microcontroller Reference Manual Rev 6 52 Freescale Semiconductor...
Page 56: ...Memory Map MPC5644A Microcontroller Reference Manual Rev 6 56 Freescale Semiconductor...
Page 1228: ...Decimation Filter MPC5644A Microcontroller Reference Manual Rev 6 1228 Freescale Semiconductor...
Page 1440: ...FlexCAN Module MPC5644A Microcontroller Reference Manual Rev 6 1440 Freescale Semiconductor...