NXP Semiconductors MPC5644A, Reference Manual, Page: 1124 / 1735

Enhanced Queued Analog-to-Digital Converter (EQADC)
MPC5644A Microcontroller Reference Manual, Rev. 6
1124 Freescale Semiconductor
The ADC conversion speed (in K samples per second - Ksps) is calculated by the following formula. T he
number of sampling cycles is determined by the LST bits in the command message - see Section ,
Conversion Command Format for the Standard Configuration ” - and it can take one of the following
values: 2, 8, 64, or 128 ADC clock cycles. The number of AD conversion cycles is 13 for differential
conversions and 14 for single-ended 12-bit resolution and unitary input gain. The maximum conversion
speed is achieved when the ADC Clock frequency is set to its maximum (15 MHz) and the number of
sampling cycles set to its minimum (2 cycles). The maximum conversion speed for differential and
single-ended conversions are 1Msps and 937.5Ksps, respectively.
Table 25-65 shows an example of how the ADC0/1_CLK_PS can be set when using a 120 MHz system
clock and the corresponding conversion speeds for all possible ADC clock frequencies. The table also
shows that according to the system clock frequency, certain clock divide factors are invalid (2, 4, 6, 8 clock
divide factors in the example) since their use would result in a ADC clock frequency higher than the
maximum one supported by the ADC. ADC clock frequency must not exceed 15 MHz.
Table 25-65. ADC Clock Configuration Example (System Clock Frequency=120 MHz)
ADC0/1_CLK_PS [0:4]
ADC0/1_
ODD_PS System Clock
Divide Factor
ADC Clock
(System Clock =
120 MHz)
Differential
Conversion Speed
with Default
Sampling Time (2
cycles)
Single-Ended
Conversion Speed
with Default
Sampling Time (2
cycles)
0b00000 0 2 N/A N/A N/A
1 3 N/A N/A N/A
0b00001 0 4 N/A N/A N/A
1 5 N/A N/A N/A
0b00010 0 6 N/A N/A N/A
1 7 N/A N/A N/A
0b00011 0 8 15.0 MHz 1.0 Msps 938 Ksps
1 9 13.3 MHz 889 Ksps 833 Ksps
0b00100 0 10 12.0 MHz 800 Ksps 750 Ksps
1 11 10.9 MHz 727 Ksps 682 Ksps
0b00101 0 12 10.0 MHz 667 Ksps 625 Ksps
1 13 9.23 MHz 615 Ksps 577 Ksps
0b00110 0 14 8.57 MHz 571 Ksps 536 Ksps
1 15 8.0 MHz 533 Ksps 500 Ksps
0b00111 0 16 7.5 MHz 500 Ksps 469 Ksps
1 17 7.06 MHz 471 Ksps 441 Ksps
0b01000 0 18 6.67 MHz 444 Ksps 417 Ksps
1 19 6.32 MHz 421 Ksps 395 Ksps
0b01001 0 20 6.0 MHz 400 Ksps 375 Ksps
1 21 5.71 MHz 381 Ksps 357 Ksps
ADCConversionSpeed
ADCClockFrequency MHz
 
NumberOfSamplingCycles NumberOfADConversionCycles +
 
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