NXP Semiconductors MPC5644A, Reference Manual, Page: 93 / 1735

Resets
MPC5644A Microcontroller Reference Manual, Rev. 6
Freescale Semiconductor 93
Chapter 4
Resets
NOTE
Throughout this text the phrase “reset configuration pins” is used to refer to
WKPCFG, BOOTCFG, and PLLREF pins.
Not all packages have BOOTCFG[0]. In this case, BOOTCFG[0] is
sampled as 0b0.
4.1 Reset sources
This device supports the following system reset sources:
• Power-on Reset
• External Reset
• Loss of Lock Reset
• Loss of Clock Reset
• Watchdog Timer/Debug Reset
• JTAG Reset
• Software System Reset
• Software External Reset (resets external resources but not the device)
All reset sources are processed by the reset controller, which monitors the reset input sources, and upon
detection of a reset event, resets internal logic and controls the assertion of the RSTOUT pin. The Software
External Reset only causes the RSTOUT pin to be asserted for a number of clock cycles determined by the
PLL mode (refer to
Section 4.3.2, RSTOUT ), and does not reset the device.
For all reset sources, the BOOTCFG[0:1] and PLLREF signals are used to determine the boot mode and
configuration of the FMPLL, respectively.
Table 4-1 shows the options for BOOTCFG[0:1] and Table 4-2
for PLLCFG[0:2]. Refer to Chapter 17, Frequency-modulated phase locked loop (FMPLL) , for
information on the FMPLL during reset.
Table 4-1. BOOTCFG options
BOOTCFG[0]
BOOTCFG[1
]
Meaning
0 0 Boot from internal flash memory
0 1 FlexCAN / eSCI boot
1 0 Boot from external memory (no arbitration)
1
1
This mode is only available in packages that have an EBI.
1 1 Reserved