NXP Semiconductors MPC5644A, Reference Manual, Page: 114 / 1735

Operating Modes and Clocking
MPC5644A Microcontroller Reference Manual, Rev. 6
114 Freescale Semiconductor
5.3.4.5.2 Halt clock gating
Software controlled clock gating can be done via the centralized halt mechanism. The SIU_HLT register
bits corresponding to individual modules are configured to determine which modules are clock gated.
The SIU_HLT register bits are used to drive a stop request signal to the modules. After the module
completes a clean shut down, the module asserts a stop acknowledge handshake signal that is used to gate
the clock to the module (see
Figure 5-7 ). The stop acknowledge signals are also captured in the
SIU_HLTACK read-only register bits.
The halted modules recover when the corresponding SIU_HLT register bit is cleared by software. Once
the bit is cleared, logic will re-enable the clocks to the modules and then negate the stop request signal after
the required timing has been met.
5.3.4.5.3 CPU clock gating
The SIU_HLT register has a bit to halt the clock to the CPU, but in order to prevent accidental CPU halting,
a stop request is only activated if the CPU is in wait state due to the execution of the WAIT instruction.
NOTE
To gate the CPU clock you need to first program the SIU_HLT register bit
assigned for CPU and then execute the CPU WAIT instruction.
Table 5-2. MDIS support
1
1
The MDIS bit default reset value is zero.
Block name Register name Bit name
DSPI_B DSPI_B_MCR MDIS
DSPI_C DSPI_C_MCR MDIS
DSPI_D DSPI_D_MCR MDIS
EBI EBI_MCR MDIS
eTPU ETPUECR_1 MDIS
FlexCAN A FLEXCAN_A_MCR MDIS
FlexCAN B FLEXCAN_B_MCR MDIS
FlexCAN C FLEXCAN_C_MCR MDIS
eMIOS EMIOS_MCR MDIS
eSCI_A eSCI_A_SCICR3 MDIS
eSCI_B eSCI_B_SCICR3 MDIS
eSCI_C eSCI_C_SCICR3 MDIS
Decimation Filter DECFILTERMCR MDIS
Red Line Module TBD MDIS
NPC NPC_PCR MCKO_EN, MCKO_GT
Flash Memory Array FLASH_MCR STOP